On 04/08/15 11:23, Gabriele Paoloni wrote:
Hi James
Please see [PATCH v6] PCI: Store PCIe bus address in struct of_pci_range
I think if you apply this patch your problem should be solved...
If you follow the discussion you see that this patch is going to be part
of the next designware
Add the SPDIF transceiver controller and pin for RK3188
Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk
---
Changes in v2:
- Sort the spdif node properties
- Drop the 0x prefix from the node name
- Rename the spdif@ node to sound@
arch/arm/boot/dts/rk3188.dtsi | 22
-Original Message-
From: James Morse [mailto:james.mo...@arm.com]
Sent: Tuesday, August 04, 2015 11:40 AM
To: Gabriele Paoloni; Wangzhou (B)
Cc: Bjorn Helgaas; Jingoo Han; Pratyush Anand; Arnd Bergmann; Lorenzo
Pieralisi; Liviu Dudau; thomas.petazz...@free-electrons.com; Jason
Guenter Roeck li...@roeck-us.net writes:
On 08/03/2015 08:22 AM, Punit Agrawal wrote:
thermal_zone_of_sensor_register is documented as returning a pointer
to either a valid thermal_zone_device on success, or a corresponding
ERR_PTR() value.
In contrast, the function returns NULL when
This enables the SPDIF optical audio output on the Radxa Rock
Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk
---
Changes in v2: None
arch/arm/boot/dts/rk3188-radxarock.dts | 19 +++
1 file changed, 19 insertions(+)
diff --git
Add devicetree bindings for the spdif tranceiver found on
found on rk3066, rk3188 and rk3288 SoCs
Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk
---
Changes in v2: None
.../devicetree/bindings/sound/rockchip-spdif.txt | 41 ++
1 file changed, 41 insertions(+)
This patchset adds support for the Rockchip SPDIF transceiver as present
on RK3066, RK3188 and RK3288 boards and enables it on a Radxa rock pro.
Tested on a Radxa Rock Pro board.
Changes in v2:
- Remove platform: module alias as it was unused
- Call MODULE_DEVICE_TABLE(of, ) right after the of
Initial version of DTSI for ProXstream2 and PH1-LD6b and DTS for
PH1-LD6b reference board.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts | 105 +++
Add I2C controller device nodes for PH1-sLD3, PH1-LD4, PH1-sLD8
(FIFO-less I2C) and PH1-Pro4 (FIFO-builtin I2C).
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts | 8 +++
arch/arm/boot/dts/uniphier-ph1-ld4.dtsi | 58
Add Clock Domain support to the R-Car M1A Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the
Hi all,
This patch series adds Clock Domain support to the Clock Pulse Generator
(CPG) Module Stop (MSTP) Clocks driver using the generic PM Domain, to
be used on shmobile SoCs without device power domains (R-Car Gen1 and
Gen2, RZ). This allows to power-manage the module clocks of SoC
The R-Mobile PM Domain driver manages both power domains and a clock
domain.
The clock domain part is very similar to the CPG/MSTP Clock Domain,
which is used on shmobile SoCs without device power domains, except for
the way how clocks suitable for power management are selected:
- The former
Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the
Add an appropriate #power-domain-cells property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add power-domains properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC
Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
manage a device.
Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
the Bus State Controller (BSC) is not power-managed by an MSTP clock,
but by a plain CPG clock (zb_clk). Add a special case to handle
Add an appropriate #power-domain-cells property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add power-domains properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC
Add Clock Domain support to the Clock Pulse Generator (CPG) Module Stop
(MSTP) Clocks driver using the generic PM Domain. This allows to
power-manage the module clocks of SoC devices that are part of the
CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume.
SoC devices that are
Add an appropriate #power-domain-cells property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add power-domains properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC
On Tue, Aug 4, 2015 at 2:22 PM, Laurent Pinchart
laurent.pinch...@ideasonboard.com wrote:
On Monday 03 August 2015 01:53:23 Kuninori Morimoto wrote:
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -0,0 +1,93 @@
+/ {
+ clocks {
Let's try to make it right from the start
Add an appropriate #power-domain-cells property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add power-domains properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC
This patch adds fixed clocks support by using CCF fixed-rate
clock implementation.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
---
drivers/clk/mediatek/clk-mtk.c | 23 +++
drivers/clk/mediatek/clk-mtk.h | 17 +
2 files changed, 40 insertions(+)
diff
On August 03, 2015 18:26, Sebastian Reichel wrote:
+MODULE_LICENSE(GPL);
MODULE_LICENSE(GPL v2);
If I do this then I need to update the file license disclaimer at the top,
as
right now they match and are correct as far as I can tell. Is this change
needed
and if so is this
Hi Maxime,
Maxime Ripard schrieb am 03.08.2015 11:34:
On Mon, Aug 03, 2015 at 11:03:52AM +0200, Timo Sigurdsson wrote:
Julian Calaby schrieb am 03.08.2015 06:22:
My only real objection here is are there boards that can go down to
0.9v and if so, won't this change make them less power
For MT6580 SoC platform, the secondary cores are in powered off state
as default, so compared with MT6589, one new enable method is needed.
This method using the SPM (System Power Manager) inside the SCPSYS to
control the CPU power.
Signed-off-by: Scott Shu scott@mediatek.com
---
We enable GTP6 which ungates the arch timer clock.
Signed-off-by: Scott Shu scott@mediatek.com
---
arch/arm/mach-mediatek/mediatek.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-mediatek/mediatek.c
b/arch/arm/mach-mediatek/mediatek.c
index
Add support for cpu enable-method mediatek,mt6580-smp for booting
secondary CPUs on MT6580.
Signed-off-by: Scott Shu scott@mediatek.com
---
arch/arm/mach-mediatek/platsmp.c | 137 ++
1 file changed, 137 insertions(+)
diff --git
-Original Message-
From: Bastien Nocera [mailto:had...@hadess.net]
Sent: 03 August, 2015 13:30
To: Tirdea, Irina; Dmitry Torokhov; linux-in...@vger.kernel.org
Cc: Mark Rutland; Purdila, Octavian; linux-ker...@vger.kernel.org;
devicetree@vger.kernel.org
Subject: Re: [PATCH v4 0/8]
This adds a CPU power domain driver for the Mediatek SCPSYS unit on
MT6580.
Signed-off-by: Scott Shu scott@mediatek.com
---
drivers/soc/mediatek/mtk-scpsys.c | 250 +++
include/linux/soc/mediatek/scpsys.h |9 ++
2 files changed, 259 insertions(+)
This patchset adds support SMP on MediaTek MT6580 Cortex-A7 quad-core SoC.
This is based on v4.2-rc1 and following patch series:
(1) Yingjoe Chen's Add SMP bringup support for mt65xx socs [1]
(2) Mars Cheng's Add mt6580 basic chip support [2]
(3) Sascha Hauer's Mediatek SCPSYS power domain
This adds mediatek,mt6580-scpsys in the compatible properties of
SCPSYS node for MT6580 SoC.
Signed-off-by: Scott Shu scott@mediatek.com
---
.../devicetree/bindings/soc/mediatek/scpsys.txt|2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
The INFRACFG contains various infrastructure registers and the SCPSYS handles
several power management related tasks. Both are needed for SMP and CPU
hotplug on MT6580.
Signed-off-by: Scott Shu scott@mediatek.com
---
arch/arm/configs/multi_v7_defconfig |2 ++
1 file changed, 2
Add arch timer node to enable arch-timer support. MT6580 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.
This set cpu enable-method to enable SMP.
Signed-off-by: Scott Shu scott@mediatek.com
---
arch/arm/boot/dts/mt6580.dtsi | 20
This adds the SCPSYS device node to the MT6580 dtsi file.
Signed-off-by: Scott Shu scott@mediatek.com
---
arch/arm/boot/dts/mt6580.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
index 06fdf6c..40957d3 100644
---
Deprecate using phy-omap-control driver to write to the mailbox register
and start using *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/usb/omap-usb.txt |7 +-
drivers/usb/musb/omap2430.c|
Hi Philipp,
On Tue, 2015-08-04 at 10:38AM +0200, Philipp Zabel wrote:
Hi,
Am Freitag, den 31.07.2015, 09:47 -0700 schrieb Sören Brinkmann:
On Fri, 2015-07-31 at 10:09AM +0200, Michal Simek wrote:
[...]
Reviewed-by: Michal Simek michal.si...@xilinx.com
Acked-by: Sören Brinkmann
On 08/04/2015 01:37 PM, Ezequiel Garcia wrote:
Hi Daniel,
Thanks for the review!
On 4 August 2015 at 06:21, Daniel Lezcano daniel.lezc...@linaro.org wrote:
On 07/27/2015 04:02 PM, Govindraj Raja wrote:
From: Ezequiel Garcia ezequiel.gar...@imgtec.com
The Pistachio SoC provides four general
On Tue, Aug 4, 2015 at 12:27 AM, Peter Meerwald pme...@pmeerw.net wrote:
Add support for the PulsedLight LIDAR rangefinder sensor which allows
high speed (over 300Hz) distance measurements using Barker Coding within
40 meter range.
comments inline
Support only tested on the blue label rev
On Mon, Aug 3, 2015 at 11:56 PM, Matt Porter mpor...@konsulko.com wrote:
Add a driver for the MAX6675 thermocouple converter. This
device interfaces with K-type thermocouples and provides
cold-junction compensated temperature readings via a
SPI interface.
./scripts/checkpatch.pl --strict
Hi Stephen,
On Mon, Aug 03, 2015 at 02:37:52PM -0700, Stephen Boyd wrote:
On 08/03, Leo Yan wrote:
diff --git a/drivers/clk/hisilicon/clk-hi6220-stub.c
b/drivers/clk/hisilicon/clk-hi6220-stub.c
new file mode 100644
index 000..0931666
--- /dev/null
+++
Document hisilicon,hi6220-sramctrl for SRAM controller.
Signed-off-by: Leo Yan leo@linaro.org
---
.../devicetree/bindings/arm/hisilicon/hisilicon.txt| 18 ++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
On Hi6220, there have some clocks which can use mailbox channel to send
messages to power controller to change frequency; this includes CPU, GPU
and DDR clocks.
For dynamic frequency scaling, firstly need write the frequency value to
SRAM region, and then send message to mailbox to trigger power
Document the new compatible for stub clock driver which is used for CPU
and DDR's dynamic frequency scaling.
Signed-off-by: Leo Yan leo@linaro.org
---
.../devicetree/bindings/clock/hi6220-clock.txt| 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git
Enable SRAM node and stub clock node for Hi6220; furthermore
add the CPU's clock so it will be used by cpufreq-dt driver.
Signed-off-by: Leo Yan leo@linaro.org
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git
This series adds support for hisilicon stub clock driver. On hi6220,
the bootloader needs load the firmware image and set info for OPPs;
after run into kernel, the stub clock driver is used to communicate
w/t firmware for cpu dynamic frequency scaling.
In patch series v1/v2, the stub clock driver
On Mon, 3 Aug 2015, Eric Anholt wrote:
Thomas Gleixner t...@linutronix.de writes:
On Mon, 27 Jul 2015, Eric Anholt wrote:
+/* Unmasks the IPI on the CPU wen it's first brought online. */
when
+static int bcm2836_arm_irqchip_cpu_notify(struct notifier_block *nfb,
+
Add support for the PulsedLight LIDAR rangefinder sensor which allows
high speed (over 300Hz) distance measurements using Barker Coding within
40 meter range.
comments inline
Support only tested on the blue label rev 2, but may work using low
sample frequencies on the original version.
Hi Moritz,
Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com
---
.../devicetree/bindings/reset/zynq-reset.txt | 68
++
1 file changed, 68 insertions(+)
create mode 100644
Add RTC support for i.MX6UL.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6ul.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index af865d3..b6c6c31 100644
---
Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock
is needed by USB 3.0.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-apmixed.c | 107 +
On 08/04/2015 10:09 AM, Philipp Zabel wrote:
Hi Moritz,
Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com
---
.../devicetree/bindings/reset/zynq-reset.txt | 68
++
1 file changed, 68
On 07/27/2015 04:02 PM, Govindraj Raja wrote:
From: Ezequiel Garcia ezequiel.gar...@imgtec.com
The Pistachio SoC provides four general purpose timers, and allow
to implement a clocksource driver.
This driver can be used as a replacement for the MIPS GIC and MIPS R4K
clocksources and sched
On ma, 2015-08-03 at 16:56 -0400, Matt Porter wrote:
--- /dev/null
+++ b/drivers/iio/temperature/max6675.c
+static const struct spi_device_id max6675_spi_ids[] = {
+ {max6675, 0},
+ {},
+};
+MODULE_DEVICE_TABLE(spi, max6675_spi_ids);
+MODULE_ALIAS(spi:max6675);
For the spi alias
On 07/31/2015 03:13 AM, Moritz Fischer wrote:
Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com
---
arch/arm/boot/dts/zynq-7000.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
b/arch/arm/boot/dts/zynq-7000.dtsi
index 0691508..6bebf02
This patch adds suspend function for i.MX6UL, it supports
standby and mem mode, for standby mode, SoC will
enter STOP mode only, while for mem mode, SoC will
enter STOP mode and DDR IO will be set to low power
mode.
As i.MX6UL contains a Cortex-A7 ARM core which has no
PL310, so we need to avoid
Add SRAM support for i.MX6UL, it has 128KB ocram
starting from 0x90.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6ul.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index b6c6c31..227ba6e
Initial version of UniPhier PH1-Pro5 device tree.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
arch/arm/boot/dts/uniphier-ph1-pro5.dtsi | 252 +++
1 file changed, 252 insertions(+)
create mode 100644 arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
diff
Hi Olof and Arnd,
Here are a little more updates for device trees for UniPhier SoCs.
Please consider applying this series to your ARM-SOC tree.
Thanks!
Masahiro Yamada (3):
ARM: dts: UniPhier: add I2C controller device nodes
ARM: dts: UniPhier: add PH1-Pro5 SoC support
ARM: dts:
Hi Daniel,
Thanks for the review!
On 4 August 2015 at 06:21, Daniel Lezcano daniel.lezc...@linaro.org wrote:
On 07/27/2015 04:02 PM, Govindraj Raja wrote:
From: Ezequiel Garcia ezequiel.gar...@imgtec.com
The Pistachio SoC provides four general purpose timers, and allow
to implement a
Add __init for clock registration functions, and add __initdata for
mtk_gate_regs initial structures.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
---
drivers/clk/mediatek/clk-gate.c | 2 +-
drivers/clk/mediatek/clk-mt8173.c | 6 +++---
drivers/clk/mediatek/clk-mtk.c| 13
The dpi_ck clock can be removed because it not actually used
in topckgen and subsystems.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
---
drivers/clk/mediatek/clk-mt8173.c | 1 -
include/dt-bindings/clock/mt8173-clk.h | 1 -
2 files changed, 2 deletions(-)
diff --git
Remove unused header files from MT8173, and remove unused
keywords from function declaration.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
---
drivers/clk/mediatek/clk-mt8173.c | 2 --
drivers/clk/mediatek/clk-mtk.h| 4 ++--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git
(This RFC was part of this mornings catch of my crude mail filter. So,
for what it's worth, what follows are a few random comments for the few
things I'm able to spot.)
On ma, 2015-08-03 at 09:13 +0800, Leo Yan wrote:
--- /dev/null
+++ b/drivers/mailbox/hisilicon/Kconfig
+config HISI_MBOX
+
Hi Paul,
On Tue, Aug 04, 2015 at 04:49:30PM +0800, Leo Yan wrote:
On Tue, Aug 04, 2015 at 10:30:24AM +0200, Paul Bolle wrote:
(This RFC was part of this mornings catch of my crude mail filter. So,
for what it's worth, what follows are a few random comments for the few
things I'm able to
On Tue, Aug 04, 2015 at 11:17:39AM +0200, Paul Bolle wrote:
On di, 2015-08-04 at 16:49 +0800, Leo Yan wrote:
On Tue, Aug 04, 2015 at 10:30:24AM +0200, Paul Bolle wrote:
On ma, 2015-08-03 at 09:13 +0800, Leo Yan wrote:
--- /dev/null
+++ b/drivers/mailbox/hisilicon/Kconfig
Add MMDC support for i.MX6UL.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6ul.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 227ba6e..d3c7ae1 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
On Tue, Aug 4, 2015 at 4:16 PM, James Liao jamesjj.l...@mediatek.com wrote:
This patchset is based on 4.2-rc2 and [1], and contains minor fixes and
subsystem clocks support for Mediatek MT8173.
The previous reviews can be found in [2]. The most different from previous
patchset is rebasing to
Thanks Geert,
I have tentatively queued this up in its own branch,
cpg-mstp-clock-domain-for-v4.3.
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Regards,
Igal Liberman
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, August 04, 2015 8:00 AM
To: Liberman Igal-B31950 igal.liber...@freescale.com
Cc: devicetree@vger.kernel.org; linuxppc-...@lists.ozlabs.org; Bucur
Madalin-Cristian-B32716 madalin.bu...@freescale.com;
Hi Philip,
On Tue, Aug 4, 2015 at 1:09 AM, Philipp Zabel p.za...@pengutronix.de wrote:
Hi Moritz,
Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com
---
.../devicetree/bindings/reset/zynq-reset.txt | 68
On 8/4/2015 2:28 AM, Stephen Boyd wrote:
On 08/03, Archit Taneja wrote:
@@ -93,5 +115,19 @@
sata@2900 {
status = ok;
};
+
+ nand@1ac0 {
+ status = ok;
+
+ pinctrl-0 =
On 8/4/2015 1:05 AM, Andy Gross wrote:
On Mon, Aug 03, 2015 at 10:38:18AM +0530, Archit Taneja wrote:
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja arch...@codeaurora.org
---
Hi,
Am Freitag, den 31.07.2015, 09:47 -0700 schrieb Sören Brinkmann:
On Fri, 2015-07-31 at 10:09AM +0200, Michal Simek wrote:
[...]
Reviewed-by: Michal Simek michal.si...@xilinx.com
Acked-by: Sören Brinkmann soren.brinkm...@xilinx.com
I'll assume these apply to the whole series and queue
Hi Maxime,
Maxime Ripard schrieb am 03.08.2015 11:13:
On Sun, Aug 02, 2015 at 09:23:06PM +0200, Timo Sigurdsson wrote:
sun7i-a20.dtsi contains an cpufreq operating point at 0.9 volts. Most A20
boards
(or all?), however, do not allow the voltage to go below 1.0V. Thus, raise
the
voltage for
Am Montag, den 03.08.2015, 20:23 +0200 schrieb Ralf Baechle:
On Mon, Aug 03, 2015 at 07:23:53PM +0200, Alban Bedel wrote:
Acked-by: Ralf Baechle r...@linux-mips.orgt
Philipp,
Feel free to take this through the reset tree. Or I can carry this in
the MIPS tree which is probably better
Hi Paul,
On Tue, Aug 04, 2015 at 10:30:24AM +0200, Paul Bolle wrote:
(This RFC was part of this mornings catch of my crude mail filter. So,
for what it's worth, what follows are a few random comments for the few
things I'm able to spot.)
On ma, 2015-08-03 at 09:13 +0800, Leo Yan wrote:
On 07/27/2015 04:00 PM, Govindraj Raja wrote:
From: Ezequiel Garcia ezequiel.gar...@imgtec.com
For the clock to be used (e.g. get its rate through clk_get_rate)
it should be prepared and enabled first.
Also, while the clock is enabled the driver must hold a reference to it,
so let's remove the
On 28/07/15 07:21, Zhou Wang wrote:
On 2015/7/25 11:21, Zhou Wang wrote:
This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
move related operations to dw_pcie_host_init. Also set
On 07/28/2015 11:51 AM, Ralf Baechle wrote:
Daniel,
On Mon, Jul 27, 2015 at 03:00:11PM +0100, Govindraj Raja wrote:
From: Ezequiel Garcia ezequiel.gar...@imgtec.com
The purpose of this patchset is to support CPUFreq on Pistachio SoC.
However, given Pistachio uses the MIPS GIC clocksource and
-Original Message-
From: Jingoo Han [mailto:jingooh...@gmail.com]
Sent: Tuesday, August 04, 2015 5:20 AM
To: Gabriele Paoloni
Cc: Rob Herring; Kishon Vijay Abraham I; Bjorn Helgaas; a...@arndb.de;
lorenzo.pieral...@arm.com; Wangzhou (B); robh...@kernel.org;
james.mo...@arm.com;
Hi James
Please see [PATCH v6] PCI: Store PCIe bus address in struct of_pci_range
I think if you apply this patch your problem should be solved...
If you follow the discussion you see that this patch is going to be part
of the next designware patchset...
Wang Zhou said You need apply
This patchset is based on 4.2-rc2 and [1], and contains minor fixes and
subsystem clocks support for Mediatek MT8173.
The previous reviews can be found in [2]. The most different from previous
patchset is rebasing to 4.2-rc2.
changes since v5:
- Rebase to 4.2-rc2.
- Patch Fix enabling of
Hi Maxime,
Maxime Ripard schrieb am 03.08.2015 11:47:
What regulator provides the 3.3V regulator used in the rest of this DT
then (MMC, GMAC) ?
For GMAC, there is a reg_gmac_3v3 defined in sun7i-a20-bananapi.dts [1].
MMC uses reg_vcc3v3 included from sunxi-common-regulators.dtsi. Am I
missing
Most multimedia subsystem clocks will be accessed by multiple
drivers, so it's a better way to manage these clocks in CCF.
This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT
subsystems.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
---
drivers/clk/mediatek/clk-mt8173.c
This adds the binding documentation for the mmsys, imgsys, vdecsys,
vencsys and vencltsys controllers found on Mediatek SoCs.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
---
.../bindings/arm/mediatek/mediatek,imgsys.txt | 22 ++
This patch adds device nodes providing subsystem clocks on MT8173,
includes mmsys, imgsys, vdecsys, vencsys and vencltsys.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 37
1 file changed, 37 insertions(+)
Remove the dependency from clk_null, and give all root clocks a
typical rate, include clkph_mck_o, usb_syspll_125m and hdmitx_dig_cts.
dpi_ck was removed due to no clock reference to it.
Replace parent clock of infra_cpum with cpum_ck, which is an external
clock and can be defined in the device
On di, 2015-08-04 at 16:49 +0800, Leo Yan wrote:
On Tue, Aug 04, 2015 at 10:30:24AM +0200, Paul Bolle wrote:
On ma, 2015-08-03 at 09:13 +0800, Leo Yan wrote:
--- /dev/null
+++ b/drivers/mailbox/hisilicon/Kconfig
+config HISI_MBOX
+ bool Hisilicon's Mailbox
+ depends on
Add the jedec vendor prefix for the JEDEC Solid State Technology
Association (formerly known as the Joint Electron Device Engineering
Council), which is already in use in several bindings.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
Acked-by: Brian Norris computersforpe...@gmail.com
On Tue, Aug 04, 2015 at 11:30:36AM +0200, Paul Bolle wrote:
On ma, 2015-08-03 at 16:56 -0400, Matt Porter wrote:
--- /dev/null
+++ b/drivers/iio/temperature/max6675.c
+static const struct spi_device_id max6675_spi_ids[] = {
+ {max6675, 0},
+ {},
+};
+MODULE_DEVICE_TABLE(spi,
Hello.
On 08/04/2015 03:28 PM, Geert Uytterhoeven wrote:
Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
manage a device.
Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
the Bus State Controller (BSC) is not power-managed by an MSTP clock,
but
Add an appropriate #power-domain-cells property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add power-domains properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC
Add Clock Domain support to the R-Car H1 Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the
If the default PM Domain using PM_CLK is used for PM runtime, the real
Clock Domain cannot be registered from DT later.
Hence do not enable it when running a multi-platform kernel with genpd
support on R-Car or RZ. The CPG/MSTP Clock Domain driver will take care
of PM runtime management of the
Add Clock Domain support to the RZ Clock Pulse Generator (CPG) driver
using the generic PM Domain. This allows to power-manage the module
clocks of SoC devices that are part of the CPG/MSTP Clock Domain using
Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP
Add an appropriate #power-domain-cells property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add power-domains properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC
Add an appropriate #power-domain-cells property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add power-domains properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC
EMMA Mobile EV2 doesn't have MSTP clocks. All its device drivers manage
clocks explicitly, without relying on Runtime PM, so it doesn't need the
legacy default PM Domain.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
---
v4:
- Add
On Tue, Aug 04, 2015 at 10:50:32AM +0300, Daniel Baluta wrote:
On Mon, Aug 3, 2015 at 11:56 PM, Matt Porter mpor...@konsulko.com wrote:
Add a driver for the MAX6675 thermocouple converter. This
device interfaces with K-type thermocouples and provides
cold-junction compensated temperature
This patch documents the i.MX6 OCOTP device tree binding.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
.../devicetree/bindings/nvmem/imx-ocotp.txt | 20
1 file changed, 20 insertions(+)
create mode 100644
The OCOTP shadow register space is clocked by the ungated ipg root clock,
but to actually sense the fuses, the On-Chip OTP controller needs a
separate clock.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/imx6qdl.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git
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