On Monday 05 October 2015 13:44:29 Alim Akhtar wrote:
> CCing Rob Herring,
>
> Hi Arnd,
>
> On 10/01/2015 04:59 PM, Arnd Bergmann wrote:
> > On Thursday 01 October 2015 18:46:34 kbuild test robot wrote:
> >> [auto build test results on v4.3-rc3 -- if it's inappropriate base, please
> >> ignore]
CCing Rob Herring,
Hi Arnd,
On 10/01/2015 04:59 PM, Arnd Bergmann wrote:
On Thursday 01 October 2015 18:46:34 kbuild test robot wrote:
[auto build test results on v4.3-rc3 -- if it's inappropriate base, please
ignore]
config: x86_64-allmodconfig (attached as .config)
reproduce:
git
On Thu, Oct 1, 2015 at 1:15 PM, Marc MarĂ wrote:
> +Additionaly, if the DMA interface is available then a read to the DMA Address
> +will return 0x51454d5520434647 ("QEMU CFG" in big-endian format).
What does this mean?
Stefan
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On Mon, Sep 28, 2015 at 09:58:44AM +0200, Jacek Anaszewski wrote:
> Hi Rob.
>
> If you are satisfied with Simon's explanation, could you confirm
> that with your ack, please?
Hi Rob,
Please let us know your answer.
Thanks in advance.
Simon
> On 09/22/2015 11:30 AM, Simon Guinot wrote:
> >On M
The patch adds support for enable/disable of the Clockgen PLLs.
clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-pll.c | 60 -
1 file chan
Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-mux.c | 3 +
Add support for new PLL-type for stih418 A9-PLL.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih418-clock.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 148e177..ae6d997 10064
Changes in v3:
- reorganize patch 1 and 2 to avoid a break git bisect
Changes in v2:
- Add const for st_pll4600c28_418_a9 structure
- Use readl_relaxed_poll_timeout macro instead Jiffies
- Add patch to enable stih418 A9 pll via DT.
This patchset is based on '[PATCH 0/2] ST PLL fixes for 4.3'
Add support for new PLL-type for stih418 A9-PLL.
Currently the 407_A9_PLL type being used, it is corrected with this patch
4600c28 PLL allows to reach higher frequencies
so its programming algorithm is extended.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
.../devicetree/bindi
>
> This patch adds the support for Device tree bindings of extcon-gpio driver.
> The extcon-gpio device tree node must include the both 'extcon-id' and
> 'extcon-gpio' property.
>
[]
>
> Signed-off-by: Chanwoo Choi
Except for some beautification issues described below,
Signed-off-by: Myu
On Fri, 02 Oct 2015, Ingi Kim wrote:
> This patch adds device driver of Richtek RT5033 PMIC.
> The driver supports a current regulated output to drive
> white LEDs for camera flash.
>
> Signed-off-by: Ingi Kim
> ---
> drivers/leds/Kconfig | 8 ++
> drivers/leds/Makefile
This patch adds the support for Device tree bindings of extcon-gpio driver.
The extcon-gpio device tree node must include the both 'extcon-id' and
'extcon-gpio' property.
For exmaple:
usb_cable: extcon-gpio-0 {
compatible = "extcon-gpio";
extcon-id = ;
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