module).
>>
>> *The patchset was not tested on Arndale board.*
>> I don't have that board. Please test it and say if the usb3503 deferred probe
>> works fine and the issue is solved.
>
> FYI... I built this series on top of next-20151009 and using
> exynos_defconfi
This patch adds PCIe host support for HiSilicon SoC Hip05.
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Signed-off-by: liudongdong
Signed-off-by: Kefeng Wang
Signed-off-by: qiuzhenfa
---
drivers/pci/host/Kconfig | 8 ++
drivers/pci/host/Makefile| 1 +
drivers/pci/host
From: gabriele paoloni
Commit f4c55c5a3f7f ("PCI: designware: Program ATU with untranslated
address") added the calculation of PCI BUS addresses in designware,
storing them in new fields added in "struct pcie_port". This
calculation is done for every designware user even if is only
applicable to
From: gabriele paoloni
This patch is needed in order to unify the PCIe designware framework for ARM and
ARM64 architectures. In the PCIe designware unification process we are calling
pci_create_root_bus() passing a "sysdata" parameter that is the same for both
ARM and ARM64 and is of type "struct
This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
move related operations to dw_pcie_host_init.
This patch also try to use of_pci_get_host_bridge_resources for ARM32 and ARM64
according to the su
This patch adds related DTS binding document for HiSilicon PCIe host driver.
Signed-off-by: Zhou Wang
---
.../bindings/arm/hisilicon/hisilicon.txt | 17 +
.../devicetree/bindings/pci/hisilicon-pcie.txt | 44 ++
2 files changed, 61 insertions(+)
create m
This patchset adds PCIe host support for HiSilicon SoC Hip05. The PCIe hosts
use PCIe IP core from Synopsys, So this driver is based on designware PCIe
driver.
Hip05 is an ARMv8 architecture SoC. It should be able to use ARM64 PCIe API in
designware PCIe driver. So this patch also adds ARM64 supp
Signed-off-by: Zhou Wang
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7ba7ab7..944a229 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8047,6 +8047,13 @@ S: Maintained
F: Documentation/devicetree/bindings/pci/xgene-pci-msi.tx
Hi,
On Sat, Oct 10, 2015 at 9:47 AM, Adam Sampson wrote:
> The LinkSprite pcDuino v3 Nano's two USB host ports are powered by a
> single RT9701GB regulator, which has its enable input tied to the A20's
> PD2 pin, pulled up to 3v3 via a 10k resistor.
>
> However, the script.bin that shipped with t
The LinkSprite pcDuino v3 Nano's two USB host ports are powered by a
single RT9701GB regulator, which has its enable input tied to the A20's
PD2 pin, pulled up to 3v3 via a 10k resistor.
However, the script.bin that shipped with the device listed PH11 and PH3
as Vbus control pins for the two USB p
Add support for initrd on ARM arch, in case
mem= boot option change the memory size or the initrd are
not placed in low memory region, we need copy the initrd
to low memory region.
Signed-off-by: yalin wang
---
arch/arm/include/asm/fixmap.h | 1 +
arch/arm/kernel/setup.c | 70
On Sat, Oct 10, 2015 at 09:11:55AM +0800, Shawn Guo wrote:
> On Fri, Oct 09, 2015 at 05:15:30PM +0800, Shengjiu Wang wrote:
> > SPDIF_GCLK is also spdif's clock, it use a same enable bit with
> > SPDIF_ROOT_CLK,
> > We didn't separate them in clock tree before.
>
> Is it the clock described as "G
On Fri, Oct 09, 2015 at 05:15:30PM +0800, Shengjiu Wang wrote:
> SPDIF_GCLK is also spdif's clock, it use a same enable bit with
> SPDIF_ROOT_CLK,
> We didn't separate them in clock tree before.
Is it the clock described as "Global clock" in Reference Manual, SPDIF
chapter? If that's the case, y
On 10/02, Jon Mason wrote:
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 23800a1..2790f21 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -2,6 +2,7 @@ menu "Platform selection"
>
> config ARCH_BCM_IPROC
> bool "Broa
On 10/02, Jon Mason wrote:
> diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
> index e029ab3..a4602aa 100644
> --- a/drivers/clk/bcm/clk-iproc-pll.c
> +++ b/drivers/clk/bcm/clk-iproc-pll.c
> @@ -137,6 +137,18 @@ static int pll_wait_for_lock(struct iproc_pll *pll)
>
On 10/02, Jon Mason wrote:
> diff --git a/drivers/clk/bcm/clk-ns2.c b/drivers/clk/bcm/clk-ns2.c
> new file mode 100644
> index 000..1d08281
> --- /dev/null
> +++ b/drivers/clk/bcm/clk-ns2.c
> @@ -0,0 +1,290 @@
> +/*
> + * Copyright (C) 2015 Broadcom Corporation
> + *
> + * This program is free
On 10/09, Jon Mason wrote:
> On Fri, Oct 09, 2015 at 12:35:40AM -0700, Stephen Boyd wrote:
> > On 10/02, Jon Mason wrote:
> >
> > > arch/arm/boot/dts/bcm5301x.dtsi | 67
> > > -
> > > 1 file changed, 60 insertions(+), 7 deletions(-)
> > >
> > > diff --git
On 10/09, Måns Rullgård wrote:
> Stephen Boyd writes:
> >
> > Does that mean a flag day? Urgh. Pain. I'm not opposed to adding
> > a pointer, in fact it might be better for performance so that we
> > don't take a cache miss in read() functions that need to load
> > some pointer. We were talking ab
On 10/09, Måns Rullgård wrote:
> Stephen Boyd writes:
>
> > On 10/09, Rob Herring wrote:
> >>
> >> Adding a ptr to the callback seems fine to me.
> >>
> >
> > Does that mean a flag day? Urgh. Pain. I'm not opposed to adding
> > a pointer, in fact it might be better for performance so that we
>
On Thu, 2015-10-01 at 19:26 -0500, Scott Wood wrote:
> [Resending to updated e-mail address]
>
> On Tue, 2015-08-11 at 11:25 -0700, Michael Turquette wrote:
> > Hi Scott,
> >
> > Quoting Scott Wood (2015-06-18 19:49:10)
> > > The existing device tree bindings are error-prone and inflexible.
> >
On Sat, Oct 10, 2015 at 04:46:55AM +0530, Kishon Vijay Abraham I wrote:
> Hi Bjorn,
>
> On Saturday 10 October 2015 04:20 AM, Bjorn Helgaas wrote:
> > [+cc Arnd, Rob]
> >
> > On Mon, Sep 28, 2015 at 06:27:36PM +0530, Kishon Vijay Abraham I wrote:
> >> Add driver modifications in pci-dra7xx to get
Hi,
On Fri, Oct 09, 2015 at 02:27:42PM -0700, Eric Anholt wrote:
> VC4 is the GPU (display and 3D) subsystem present on the 2835 and some
> other Broadcom SoCs.
>
> This binding follows the model of msm, imx, sti, and others, where
> there is a subsystem node for the whole GPU, with nodes for the
On Thu, Oct 08, 2015 at 12:54:16PM -0700, David Daney wrote:
> From: David Daney
>
> Make the offset from the beginning of the "reg" property be from the
> starting bus number, rather than zero. Hoist the invariant size
> calculation out of the mapping for loop.
>
> Update host-generic-pci.txt
Hi,
On Saturday 10 October 2015 04:46 AM, Kishon Vijay Abraham I wrote:
> Hi Bjorn,
>
> On Saturday 10 October 2015 04:20 AM, Bjorn Helgaas wrote:
>> [+cc Arnd, Rob]
>>
>> On Mon, Sep 28, 2015 at 06:27:36PM +0530, Kishon Vijay Abraham I wrote:
>>> Add driver modifications in pci-dra7xx to get x2
Hi Bjorn,
On Saturday 10 October 2015 04:20 AM, Bjorn Helgaas wrote:
> [+cc Arnd, Rob]
>
> On Mon, Sep 28, 2015 at 06:27:36PM +0530, Kishon Vijay Abraham I wrote:
>> Add driver modifications in pci-dra7xx to get x2 mode working in
>> DRA72 and DRA74. Certain modifications is needed in PHY driver
On Thu, Oct 08, 2015 at 06:03:24PM +0800, Ley Foon Tan wrote:
> On Thu, Oct 8, 2015 at 5:47 PM, Russell King - ARM Linux
> wrote:
> >
> > On Thu, Oct 08, 2015 at 05:43:11PM +0800, Ley Foon Tan wrote:
> > > +static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
> > > +
Emil Velikov writes:
> Hi Eric,
>
> On 9 October 2015 at 22:27, Eric Anholt wrote:
>> Signed-off-by: Eric Anholt
>> ---
>>
>> v2: Mark it Supported, not Maintained.
>>
>> MAINTAINERS | 6 ++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 7ba7ab7..e
[+cc Arnd, Rob]
On Mon, Sep 28, 2015 at 06:27:36PM +0530, Kishon Vijay Abraham I wrote:
> Add driver modifications in pci-dra7xx to get x2 mode working in
> DRA72 and DRA74. Certain modifications is needed in PHY driver also
> which I'll send as a separate series.
>
> Kishon Vijay Abraham I (2):
By default, armada-370-xp.dtsi file has internal RTC enabled.
NETGEAR ReadyNAS 102, 104 and 2120 all use an Intersil ISL12057
I2C RTC chip. The internal RTC not being disabled in the .dts
files of those devices result in the following useless first
line during boot:
[4.500056] rtc-mv d0010300
This cosmetic patch reorder nodes under internal-regs by increasing
address order, as epxected.
Signed-off-by: Arnaud Ebalard
---
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 86 +-
1 file changed, 43 insertions(+), 43 deletions(-)
diff --git a/arch/arm/boot/dts/arm
Hi,
Here are two simple patches for Armada-based ReadyNAS devices.
The first one disables Armada 370/XP rtc in the .dts files of ReadyNAS
102, 104 and 2120 devices. Those use an Intersil ISL12057 I2C RTC chip
and do not use the internal Armada RTC. Because it is enabled in
included armada-370-xp.
Hi Eric,
On 9 October 2015 at 22:27, Eric Anholt wrote:
> Signed-off-by: Eric Anholt
> ---
>
> v2: Mark it Supported, not Maintained.
>
> MAINTAINERS | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7ba7ab7..e331e46 100644
> --- a/MAINTAINERS
> ++
Stephen Boyd writes:
> On 10/09, Rob Herring wrote:
>> +Stephen who has worked on this code.
>>
>> On Fri, Oct 9, 2015 at 11:19 AM, Måns Rullgård wrote:
>> > Måns Rullgård writes:
>> >
>> >> Rob Herring writes:
>> >>
>> >>> On Wed, Oct 7, 2015 at 11:47 AM, Måns Rullgård wrote:
>> What w
Enable the PCIe controller and clock for the Porter board.
This patch is analogous to the commit 485f3ce67c11 ("ARM: shmobile:
henninger: Enable PCIe Controller & PCIe bus clock") as there are no
differences between the boards in this respect.
Signed-off-by: Sergei Shtylyov
---
This patch is ag
Define the Porter board dependent part of the QSPI device node.
Add device nodes for Spansion S25FL512S SPI flash and the MTD partitions
on it.
This patch is mostly analogous to the commit f59838d44835 ("ARM:
shmobile: henninger: add QSPI DT support") as there are no differences
between the b
From: Derek Foreman
Keep the fbdev_cma pointer around so we can use it on hotplog and close
to ensure the frame buffer console is in a useful state.
Signed-off-by: Derek Foreman
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/vc4/vc4_drv.c | 14 ++
drivers/gpu/drm/vc4/vc4_drv.h |
VC4 is the GPU (display and 3D) subsystem present on the 2835 and some
other Broadcom SoCs.
This binding follows the model of msm, imx, sti, and others, where
there is a subsystem node for the whole GPU, with nodes for the
individual HW components within it.
Signed-off-by: Eric Anholt
---
v2: E
VC4 is the GPU (display and 3D) present on the 2835.
Signed-off-by: Eric Anholt
---
v2: Sort by register address, mark HDMI as disabled by default in the
SoC file and enable it from -rpi.
v3: Add references to the pixel/HSM clocks for HDMI. Rename
compatibility strings and clean up nod
From: Derek Foreman
Signed-off-by: Derek Foreman
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/vc4/vc4_kms.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index ee3e004..2e5597d 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++
This is enough for fbcon and bringing up X using
xf86-video-modesetting. It doesn't support the 3D accelerator or
power management yet.
Signed-off-by: Eric Anholt
Acked-by: Daniel Vetter
---
v2: Drop FB_HELPER select thanks to Archit's patches. Do manual init
ordering instead of using the
Signed-off-by: Eric Anholt
---
v2: Mark it Supported, not Maintained.
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7ba7ab7..e331e46 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3653,6 +3653,12 @@ S: Maintained
F: drivers/gpu/
We need to use it for getting video modes over HDMI.
Signed-off-by: Eric Anholt
Acked-by: Stephen Warren
---
v2: Mark it as disabled by default, and enable it in bcm2835-rpi.
arch/arm/boot/dts/bcm2835-rpi.dtsi | 4
arch/arm/boot/dts/bcm2835.dtsi | 10 ++
2 files changed, 14
This is a respin of the Raspberry Pi KMS series. Now that we've got a
real clock driver, I can actually set new video modes. Also in this
version, most of the custom DT stuff from before is gone, thanks to
finding exynos's platform_driver component matching code (I have sent
separate patches to d
Define the Porter board dependent part of the QSPI device node.
Add device nodes for Spansion S25FL512S SPI flash and the MTD partitions
on it.
This patch is mostly analogous to the commit f59838d44835 (ARM: shmobile:
henninger: add QSPI DT support) as there are no differences between the
boar
On 05/07/2014 12:47 AM, Sergei Shtylyov wrote:
Define the Henninger board dependent part of the MSIOF0 device node.
Add device node for Renesas R2A11302FT PMIC for which no bindings exist yet.
I've just realized that there's no such PMIC on the Henninger/Porter
boards and MSIOF0 is only co
Stephen Boyd writes:
> On 10/09, Rob Herring wrote:
>> +Stephen who has worked on this code.
>>
>> On Fri, Oct 9, 2015 at 11:19 AM, Måns Rullgård wrote:
>> > Måns Rullgård writes:
>> >
>> >> Rob Herring writes:
>> >>
>> >>> On Wed, Oct 7, 2015 at 11:47 AM, Måns Rullgård wrote:
>> What w
ve that board. Please test it and say if the usb3503 deferred probe
> works fine and the issue is solved.
FYI... I built this series on top of next-20151009 and using
exynos_defconfig. I booted it on my arndale, and I still don't see the
networking come up. Full boot log attached.
K
On 10/09, Rob Herring wrote:
> +Stephen who has worked on this code.
>
> On Fri, Oct 9, 2015 at 11:19 AM, Måns Rullgård wrote:
> > Måns Rullgård writes:
> >
> >> Rob Herring writes:
> >>
> >>> On Wed, Oct 7, 2015 at 11:47 AM, Måns Rullgård wrote:
> What would be a proper way to select a s
On Friday 09 October 2015 17:57:26 Liviu Dudau wrote:
> +/*
> + * The PLDA's XpressRICH3 doesn't describe itself as a bridge. This is
> required
> + * for correct/normal enumeration.
> + */
> +static void xr3pci_quirk_class(struct pci_dev *pdev)
> +{
> + pdev->class = PCI_CLASS_BRIDGE_PCI <<
On Friday 09 October 2015 17:10:36 Wei Xu wrote:
> Replace console with stdout-path so that we don't have to put the
> console on the kernel command line.
>
> Remove earlyprintk to allow the kernel to boot on a system even
> if DEBUG_LL is configured for another system.
>
> Signed-off-by: Wei Xu
On Fri, Oct 09, 2015 at 12:35:40AM -0700, Stephen Boyd wrote:
> On 10/02, Jon Mason wrote:
> > Replace current device tree dummy clocks with real clock support for
> > Broadcom Northstar SoCs.
> >
> > Signed-off-by: Jon Mason
> > ---
>
> I'd rather not take any dts changes through clk tree.
Ok,
On Fri, 9 Oct 2015, Greg KH wrote:
> On Fri, Oct 09, 2015 at 07:09:15PM +0100, atull wrote:
> > On Thu, 8 Oct 2015, Moritz Fischer wrote:
> >
> > > --- /dev/null
> > > +++ b/drivers/fpga/zynq-fpga.c
> > > @@ -0,0 +1,478 @@
> > > +/*
> > > + * Copyright (c) 2011-2015 Xilinx Inc.
> > > + * Copyrigh
On Thu, 8 Oct 2015, Moritz Fischer wrote:
> --- /dev/null
> +++ b/drivers/fpga/zynq-fpga.c
> @@ -0,0 +1,478 @@
> +/*
> + * Copyright (c) 2011-2015 Xilinx Inc.
> + * Copyright (c) 2015, National Instruments Corp.
> + *
> + * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
> + *
On Fri, Oct 09, 2015 at 06:41:51PM +0100, Robin Murphy wrote:
> On 09/10/15 16:57, Will Deacon wrote:
> >On Tue, Sep 22, 2015 at 03:12:47PM +0100, Yong Wu wrote:
> >> I would like to show you a problem I met, The recursion here may
> >>lead to stack overflow while we test FHD video decode.
> >
On Fri, Oct 09, 2015 at 07:09:15PM +0100, atull wrote:
> On Thu, 8 Oct 2015, Moritz Fischer wrote:
>
> > --- /dev/null
> > +++ b/drivers/fpga/zynq-fpga.c
> > @@ -0,0 +1,478 @@
> > +/*
> > + * Copyright (c) 2011-2015 Xilinx Inc.
> > + * Copyright (c) 2015, National Instruments Corp.
> > + *
> > + *
On Fri, Oct 09, 2015 at 12:03:57AM -0700, Stephen Boyd wrote:
> On 10/02, Jon Mason wrote:
> > diff --git a/drivers/clk/bcm/clk-iproc-pll.c
> > b/drivers/clk/bcm/clk-iproc-pll.c
> > index e029ab3..a4602aa 100644
> > --- a/drivers/clk/bcm/clk-iproc-pll.c
> > +++ b/drivers/clk/bcm/clk-iproc-pll.c
>
On Fri, Oct 9, 2015 at 11:12 AM, David Daney wrote:
> On 10/09/2015 06:20 AM, Rob Herring wrote:
>>
>> On Thu, Oct 8, 2015 at 5:10 PM, David Daney wrote:
>>>
>>> From: Mark Rutland
>>>
>>> Currently msi-parent is used by a few bindings to describe the
>>> relationship between a PCI root complex
On Fri, Oct 09, 2015 at 12:37:46AM -0700, Stephen Boyd wrote:
> On 10/02, Jon Mason wrote:
> > diff --git a/drivers/clk/bcm/clk-nsp.c b/drivers/clk/bcm/clk-nsp.c
> > new file mode 100644
> > index 000..708961a
> > --- /dev/null
> > +++ b/drivers/clk/bcm/clk-nsp.c
> > @@ -0,0 +1,139 @@
> > +/*
>
Hello,
this is v2 of my "Input: goodix - add axis swapping and axis inversion
support" patchset.
The goodix touchscreen driver has gained device-tree support in kernel
4.1, but doesn't currently support the touchscreen-swapped-x-y,
touchscreen-inverted-x and touchscreen-inverted-y properties.
On
The goodix touchscreen driver has gained support for the
optional touchscreen-inverted-x, touchscreen-inverted-y
and touchscreen-swapped-x-y properties as described in
Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt.
Document these properties in the goodix bindings description.
The goodix touchscreen driver uses a "rotated_screen" flag for
systems on which the touchscreen is mounted rotated by 180
degrees with respect to the display. With the addition of
support for the dt properties "touchscreen-inverted-x" and
"touchscreen-inverted-y", a separate "rotated_screen" flag
Implement support for the following device-tree properties
in the goodix touchscreen driver:
- touchscreen-inverted-x: X axis is inverted (boolean)
- touchscreen-inverted-y: Y axis is inverted (boolean)
- touchscreen-swapped-x-y: X and Y axis are swapped (boolean)
These are necessary on tabl
+Stephen who has worked on this code.
On Fri, Oct 9, 2015 at 11:19 AM, Måns Rullgård wrote:
> Måns Rullgård writes:
>
>> Rob Herring writes:
>>
>>> On Wed, Oct 7, 2015 at 11:47 AM, Måns Rullgård wrote:
What would be a proper way to select a sched_clock source? I realise
it's a Linux
Hello.
On 10/09/2015 04:13 AM, Simon Horman wrote:
Define the Porter board dependent part of the I2C2 device node.
This patch is analogous to the commit 29a647c396a0 ("ARM: shmobile:
henninger: add I2C2 DT support") as there are no differences between
the boards in this respect.
Signed-off-b
On Fri, Oct 9, 2015 at 12:04 PM, Mark Rutland wrote:
> On Fri, Oct 09, 2015 at 05:57:28PM +0100, Liviu Dudau wrote:
>> Juno R1 board sports a functional PCIe host bridge that is
>> compliant with the SBSA standard found [1] here. With the right
>> firmware that initialises the XpressRICH3 controll
On 09/10/15 16:57, Will Deacon wrote:
On Tue, Sep 22, 2015 at 03:12:47PM +0100, Yong Wu wrote:
I would like to show you a problem I met, The recursion here may
lead to stack overflow while we test FHD video decode.
From the log, I get the internal variable in the error case: the
"siz
On Mon, Sep 21, 2015 at 10:59 PM, Matt Porter wrote:
> Documentation explaining the syntax and format of the YAML-based DT binding
> documentation.
>
> Signed-off-by: Matt Porter
> ---
> .../devicetree/bindings/dt-binding-format.txt | 105
> +
> 1 file changed, 105 inse
Hi Josh,
thanks for the review!
On Fri, Oct 9, 2015 at 6:33 PM, Josh Cartwright wrote:
> Hey Moritz-
>
> On Fri, Oct 09, 2015 at 12:45:07AM +0200, Moritz Fischer wrote:
>> This commit adds FPGA Manager support for the Xilinx Zynq chip.
>> The code heavily borrows from the xdevcfg driver in Xilin
On Fri, Oct 09, 2015 at 05:57:28PM +0100, Liviu Dudau wrote:
> Juno R1 board sports a functional PCIe host bridge that is
> compliant with the SBSA standard found [1] here. With the right
> firmware that initialises the XpressRICH3 controller one can
> use the generic Host Bridge driver to use the
On Fri, Oct 09, 2015 at 05:59:29PM +0100, Mark Rutland wrote:
> On Fri, Oct 09, 2015 at 05:57:27PM +0100, Liviu Dudau wrote:
> > Use "plda" as vendor prefix for PLDA.
> >
> > Signed-off-by: Liviu Dudau
>
> Having looked on PLDA's website it seems "PLDA" is their preferred name,
> and I can't fin
On Fri, Oct 09, 2015 at 05:57:27PM +0100, Liviu Dudau wrote:
> Use "plda" as vendor prefix for PLDA.
>
> Signed-off-by: Liviu Dudau
Having looked on PLDA's website it seems "PLDA" is their preferred name,
and I can't find any suffix used, so this looks fine to me:
Acked-by: Mark Rutland
Mark.
From: Andrew Murray
Signed-off-by: Liviu Dudau
---
include/linux/pci_ids.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index d9ba49c..1542b2b 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1319,6 +1319,9 @@
#d
The XpressRICH3 host bridge at power up has an unassigned class on
some of ARM Ltd boards, add a quirk to correct that.
Signed-off-by: Liviu Dudau
---
drivers/pci/quirks.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index b03373f..a
Juno R1 board sports a functional PCIe host bridge that is
compliant with the SBSA standard found [1] here. With the right
firmware that initialises the XpressRICH3 controller one can
use the generic Host Bridge driver to use the PCIe hardware.
Signed-off-by: Liviu Dudau
[1] http://infocenter.ar
Changes in v2 vs v1:
- Add plda as OF vendor prefix
- Add more specific compatible values to the Juno R1 DT
Juno R1 board has a working PCIe host bridge that can be enabled and
configured by the firmware and made use of by Linux. For UEFI, the
Linaro releases contain firmware that configure th
Now that pci-host-generic can be used under arm64, enable it by
default so that SBSA compliant systems can use it.
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Liviu Dudau
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/
Use "plda" as vendor prefix for PLDA.
Signed-off-by: Liviu Dudau
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 82d2
Hi Catalin,
On Fri, Oct 9, 2015 at 8:48 PM, Catalin Marinas wrote:
> On Fri, Aug 14, 2015 at 10:09:33PM +0530, Ganapatrao Kulkarni wrote:
>> Adding dt node pasring for numa topology using property arm,associativity.
>> arm,associativity property can be used to map memory, cpu and
>> io devices t
On Fri, Oct 09, 2015 at 05:32:52PM +0100, Mark Rutland wrote:
> On Fri, Oct 09, 2015 at 05:09:10PM +0100, Liviu Dudau wrote:
> > On Fri, Oct 09, 2015 at 05:49:18PM +0200, Arnd Bergmann wrote:
> > > On Friday 09 October 2015 16:44:08 Mark Rutland wrote:
> > > > On Fri, Oct 09, 2015 at 03:11:07PM +01
Hi Vinod,
On Fri, Oct 9, 2015 at 9:42 PM, Vinod Koul wrote:
> On Thu, Oct 08, 2015 at 02:36:57PM +0530, Rameshwar Prasad Sahu wrote:
>> The DMA engine supports memory copy, RAID5 XOR, RAID6 PQ, and other
>> computations. But the bandwidth of the entire DMA engine is shared
>> among all channels.
Hey Moritz-
On Fri, Oct 09, 2015 at 12:45:07AM +0200, Moritz Fischer wrote:
> This commit adds FPGA Manager support for the Xilinx Zynq chip.
> The code heavily borrows from the xdevcfg driver in Xilinx'
> vendor tree.
>
> Signed-off-by: Moritz Fischer
[..]
> +++ b/drivers/fpga/zynq-fpga.c
[..]
On Fri, Oct 09, 2015 at 05:09:10PM +0100, Liviu Dudau wrote:
> On Fri, Oct 09, 2015 at 05:49:18PM +0200, Arnd Bergmann wrote:
> > On Friday 09 October 2015 16:44:08 Mark Rutland wrote:
> > > On Fri, Oct 09, 2015 at 03:11:07PM +0100, Liviu Dudau wrote:
> > > > On Fri, Oct 09, 2015 at 08:54:33AM -050
On Thu, 2015-10-08 at 14:38 -0700, Yinghai Lu wrote:
> For device resource PREF bit setting under bridge 64-bit pref resource,
> we need to make sure only set PREF for 64bit resource, so set
> IORESOUCE_MEM_64 for 64bit resource during OF device resource flags
> parsing.
>
> Link: https://bugzilla
Måns Rullgård writes:
> Rob Herring writes:
>
>> On Wed, Oct 7, 2015 at 11:47 AM, Måns Rullgård wrote:
>>> What would be a proper way to select a sched_clock source? I realise
>>> it's a Linux-specific thing and DT is supposed to be generic, but the
>>> information must be provided somehow.
>>
On Thu, Oct 08, 2015 at 02:36:57PM +0530, Rameshwar Prasad Sahu wrote:
> The DMA engine supports memory copy, RAID5 XOR, RAID6 PQ, and other
> computations. But the bandwidth of the entire DMA engine is shared
> among all channels. This patch re-configures operations availability
> such that one ca
On 10/09/2015 06:20 AM, Rob Herring wrote:
On Thu, Oct 8, 2015 at 5:10 PM, David Daney wrote:
From: Mark Rutland
Currently msi-parent is used by a few bindings to describe the
relationship between a PCI root complex and a single MSI controller, but
this property does not have a generic bindin
Replace console with stdout-path so that we don't have to put the
console on the kernel command line.
Remove earlyprintk to allow the kernel to boot on a system even
if DEBUG_LL is configured for another system.
Signed-off-by: Wei Xu
Tested-by: Zhangfei Gao
---
arch/arm/boot/dts/hi3620-hi4511.
On Fri, Oct 09, 2015 at 05:49:18PM +0200, Arnd Bergmann wrote:
> On Friday 09 October 2015 16:44:08 Mark Rutland wrote:
> > On Fri, Oct 09, 2015 at 03:11:07PM +0100, Liviu Dudau wrote:
> > > On Fri, Oct 09, 2015 at 08:54:33AM -0500, Rob Herring wrote:
> > > Or maybe I can claim the use of the strin
On Fri, Oct 09, 2015 at 12:45:05AM +0200, Moritz Fischer wrote:
> Signed-off-by: Moritz Fischer
> ---
> .../bindings/fpga/xilinx-zynq-fpga-mgr.txt | 26
> ++
> 1 file changed, 26 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/fpga/xilinx-zynq
On Thu, 8 Oct 2015 17:23:42 +0300
Irina Tirdea wrote:
> Add several enhancements to the Goodix touchscreen driver.
>
> The new functionality is only available for devices that
> declare named gpio pins for interrupt and reset in their
> ACPI/DT configuration.
>
I tested this patchset on ARM t
On Tue, Sep 22, 2015 at 03:12:47PM +0100, Yong Wu wrote:
> I would like to show you a problem I met, The recursion here may
> lead to stack overflow while we test FHD video decode.
>
> From the log, I get the internal variable in the error case: the
> "size" is 0x10, the "iova" is 0xf
On Friday 09 October 2015 16:44:08 Mark Rutland wrote:
> On Fri, Oct 09, 2015 at 03:11:07PM +0100, Liviu Dudau wrote:
> > On Fri, Oct 09, 2015 at 08:54:33AM -0500, Rob Herring wrote:
> > Or maybe I can claim the use of the string on account on being the first on
> > arm64
> >
> > I can add a ven
On Fri, Oct 09, 2015 at 03:11:07PM +0100, Liviu Dudau wrote:
> On Fri, Oct 09, 2015 at 08:54:33AM -0500, Rob Herring wrote:
> > On Fri, Oct 9, 2015 at 8:45 AM, Liviu Dudau wrote:
> > > Juno R1 board sports a functional PCIe host bridge that is
> > > compliant with the SBSA standard found here[1].
On Fri, Aug 14, 2015 at 10:09:33PM +0530, Ganapatrao Kulkarni wrote:
> Adding dt node pasring for numa topology using property arm,associativity.
> arm,associativity property can be used to map memory, cpu and
> io devices to numa node.
>
> Signed-off-by: Ganapatrao Kulkarni
> ---
> arch/arm64/K
Add the blue status LED to the Hardkernel Odroid C1 board DTS.
This is the only programmable LED on the board.
Signed-off-by: Edward Cragg
---
arch/arm/boot/dts/meson8b-odroidc1.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts
b/arch/
Add status LED for Hardkernel Odroid-C1 development board
Edward Cragg (1):
ARM: meson: Add status LED for Odroid-C1
arch/arm/boot/dts/meson8b-odroidc1.dts | 13 +
1 file changed, 13 insertions(+)
--
2.5.0
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On Thu, 2015-10-08 at 17:23 +0300, Irina Tirdea wrote:
> After power on, it is recommended that the driver resets the device.
> The reset procedure timing is described in the datasheet and is used
> at device init (before writing device configuration) and
> for power management. It is a sequence of
On Thu, 2015-10-08 at 17:23 +0300, Irina Tirdea wrote:
> Add several enhancements to the Goodix touchscreen driver.
>
> The new functionality is only available for devices that
> declare named gpio pins for interrupt and reset in their
> ACPI/DT configuration.
You can add
Tested-by: Bastien Noc
On Fri, Oct 09, 2015 at 08:54:33AM -0500, Rob Herring wrote:
> On Fri, Oct 9, 2015 at 8:45 AM, Liviu Dudau wrote:
> > Juno R1 board sports a functional PCIe host bridge that is
> > compliant with the SBSA standard found here[1]. With the right
> > firmware that initialises the XpressRICH3 controll
On 09/10/15 14:47, Bharat Kumar Gogada wrote:
>> Hi Bharat,
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>>>
>>> +/* SSPL ERROR */ +#define SLVERR 0x02
>>> +#define DECERR
>>> 0x03 + +struct nwl_msi {/* struct nwl_msi - MSI
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