i.MX6UL can be powered off by programming SNVS.
When long press ON/OFF button(5 seconds),
PMIC_ON_REQ pin will be set to low and external
PMIC will be powered off.
And system can be powered on by long press ON/OFF
button again.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot
On Thu, Aug 06, 2015 at 03:41:34PM +0800, Shawn Guo wrote:
On Wed, Aug 05, 2015 at 09:57:55PM +0800, Anson Huang wrote:
Commit(def56bb input: snvs_pwrkey: use wakeup-source
as deivce tree property name) replaces the property name
of wakeup with wakeup-source, update this change
in i.MX6SX
Commit(def56bb input: snvs_pwrkey: use wakeup-source
as deivce tree property name) replaces the property name
of wakeup with wakeup-source, update this change
in i.MX6SX dtsi accordingly.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6sx.dtsi | 2 +-
1 file changed, 1
Add i.MX6UL SNVS power key support.
Signed-off-by: Anson Huang b20...@freescale.com
---
This patch is based on my last patch under review:
(ARM: dts: imx6ul: add RTC support).
arch/arm/boot/dts/imx6ul.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi
Add RTC support for i.MX6UL.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6ul.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index af865d3..b6c6c31 100644
--- a/arch/arm/boot/dts
any PL310 operations during
suspend/resume, also, we need to flush Cortex-A7's inernal
L2 cache before suspend.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/mach-imx6ul.c | 2 ++
arch/arm/mach-imx/pm-imx6.c | 46
Add SRAM support for i.MX6UL, it has 128KB ocram
starting from 0x90.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6ul.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index b6c6c31..227ba6e
Add MMDC support for i.MX6UL.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6ul.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 227ba6e..d3c7ae1 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
Enable GPC as extended interrupt controller of
GIC, as GPC needs to manage wakeup source for
low power modes.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6ul.dtsi | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b
Add basic i.MX6SoloX Sabre Auto board support, currently
only debug UART and uSDHC are supported on this board.
Signed-off-by: Anson Huang b20...@freescale.com
---
change since V1:
1. correct gpio regulator node;
2. using macro define for GPIO active value;
3. improve
Add basic i.MX6SoloX Sabre Auto board support, currently
only debug UART and uSDHC are supported on this board.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/imx6sx-sabreauto.dts | 135
2
;
LDO bypassed(min value):
996MHz: VDDARM: 1.250V, VDDSOC: 1.150V;
792MHz: VDDARM: 1.150V, VDDSOC: 1.150V;
396MHz: VDDARM: 1.050V, VDDSOC: 1.150V;
Adding 25mV to cover board IR drop, for LDO enabled
mode of 996MHz, VDDARM should be 1.250V, so this
patch updates it.
Signed-off-by: Anson Huang b20
Add gpt_3m clock for i.mx6qdl, as gpt can source clock
from OSC, some i.MX6 series SOCs has fixed divider of
8 for gpt clock, so here add a fix clk of gpt_3m.
i.MX6Q TO1.0 has no gpt_3m option, so force it to be
from ipg_per.
Signed-off-by: Anson Huang b20...@freescale.com
---
change log from v2
GPT_CR_24MEM to
enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
is for pre-scaling of this OSC clk, here set it to 8
to make gpt per clk is 3MHz;
i.MX6SL: ipg_per can be from OSC directly, so no need to
implement this new clk source for gpt per.
Signed-off-by: Anson Huang b20
and all i.MX6dl SoC.
On i.mx6sx, just make gpt per clk from OSC.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6qdl.dtsi |5 +++--
arch/arm/boot/dts/imx6sx.dtsi |2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b
.
Anson Huang (3):
ARM: imx: add gpt_3m clk for i.mx6qdl
ARM: dts: imx6: make gpt per clock can be from OSC
ARM: imx: source gpt per clk from OSC for system timer
arch/arm/boot/dts/imx6qdl.dtsi|5 ++--
arch/arm/boot/dts/imx6sx.dtsi |2 +-
arch/arm/mach-imx/clk
and all i.MX6dl SoC.
On i.mx6sx, just make gpt per clk from OSC.
Signed-off-by: Anson Huang b20...@freescale.com
---
change log from v1 - v2
on i.mx6q TO1.0, there is no OSC clk source for
gpt per, so I have to add a new clk source of
osc_per for gpt to cover i.mx6q TO1.0
GPT_CR_24MEM to
enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
is for pre-scaling of this OSC clk, here set it to 8
to make gpt per clk is 3MHz;
i.MX6SL: ipg_per can be from OSC directly, so no need to
implement this new clk source for gpt per.
Signed-off-by: Anson Huang b20
Original gpt per clk parent is from ipg_per clk which
may be scaled when system enter low bus mode, as ipg
clk will be lower in low bus mode, to keep system clk
NOT drift, select gpt per clk parent from OSC which
is at fixed freq always.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch
to
implement this new clk source for gpt per.
Anson Huang (3):
ARM: imx: add gpt_3m clk for i.mx6qdl
ARM: dts: imx6: change gpt per clk to gpt_3m on i.mx6qdl and i.mx6sx
ARM: imx: source gpt per clk from OSC for system timer
arch/arm/boot/dts/imx6qdl.dtsi|2 +-
arch/arm/boot/dts
Add gpt_3m clock for i.mx6qdl, as gpt can source clock
from OSC, some i.MX6 series SOCs has fixed divider of
8 for gpt clock, so here add a fix clk of gpt_3m.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/mach-imx/clk-imx6q.c |1 +
include/dt-bindings/clock/imx6qdl
GPT_CR_24MEM to
enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
is for pre-scaling of this OSC clk, here set it to 8
to make gpt per clk is 3MHz;
i.MX6SL: ipg_per can be from OSC directly, so no need to
implement this new clk source for gpt per.
Signed-off-by: Anson Huang b20
we need to correct it before enabling thermal irq;
Enable PANIC ALARM as critical trip point, it will trigger
system reset via SRC module once PANIC IRQ is triggered, it
is pure hardware function, so use it instead of software
reset by cooling device.
Signed-off-by: Anson Huang b20
Add thermal sensor support for i.MX6SL.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6sl.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c75800c..505da9e 100644
On Tue, Aug 05, 2014 at 09:25:53AM -0400, Eduardo Valentin wrote:
Hello Anson,
On Tue, Aug 05, 2014 at 05:12:43PM +0800, Anson Huang wrote:
i.MX6SX has some new features of thermal interrupt function,
there are LOW, HIGH and PANIC irq for thermal sensor, so add
platform data to separate
-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6sx.dtsi |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 78ccf61..7b41194 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts
This patch adds support for imx6sx-sdb board's gpio keys:
SW4(FUNC1): KEY_VOLUMEUP
SW5(FUNC2): KEY_VOLUMEDOWN
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6sx-sdb.dts | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts
Add initial imx6sx sdb board support with uart and usdhc enabled.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6sx-sdb.dts | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6sx-sdb.dts
diff --git
Add device tree support for i.MX6SoloX SOC.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6sx.dtsi | 524 +
1 file changed, 524 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6sx.dtsi
diff --git a/arch/arm/boot/dts
Add device tree support for i.MX6SoloX SOC.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6sx.dtsi | 524 +
1 file changed, 524 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6sx.dtsi
diff --git a/arch/arm/boot/dts
Add initial imx6sx sdb board support with uart and usdhc enabled.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6sx-sdb.dts | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6sx-sdb.dts
diff --git
The fuse map of speed_grading[1:0] defines the max speed
of ARM, see below the definition:
2b'11: 12Hz;
2b'10: 99600Hz;
2b'01: 85200Hz; -- i.MX6Q Only, exclusive with 996MHz.
2b'00: 79200Hz;
Need to remove all illegal setpoints according to fuse
map.
Signed-off-by: Anson
According to datasheet, i.MX6Q has setpoint of 852MHz
which is exclusive with 996MHz, the fuse map of speed_grading
defines the max speed of ARM, here we add this 852MHz
setpoint opp info, kernel will check the speed_grading
fuse and remove all illegal setpoints.
Signed-off-by: Anson Huang b20
According to datasheet, i.MX6Q has setpoint of 852MHz
which is exclusive with 996MHz, the fuse map of speed_grading
defines the max speed of ARM, here we add this 852MHz
setpoint opp info, kernel will check the speed_grading
fuse and remove all illegal setpoints.
Signed-off-by: Anson Huang b20
The fuse map of speed_grading[1:0] defines the max speed
of ARM, see below the definition:
2b'11: 12Hz;
2b'10: 99600Hz;
2b'01: 85200Hz; -- i.MX6Q Only, exclusive with 996MHz.
2b'00: 79200Hz;
Need to remove all illegal setpoints according to fuse
map.
Signed-off-by: Anson
From schematic, the power, vol+/- key's active state is low,
so we need to set the gpio flag to active low.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6qdl-sabresd.dtsi |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts
From schematic, the power, vol+/- key's active state is low,
so we need to set the gpio flag to active low.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6qdl-sabresd.dtsi |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts
On Tue, Jan 14, 2014 at 04:29:50PM +0800, Shawn Guo wrote:
On Tue, Jan 14, 2014 at 03:37:09PM +0800, Anson Huang wrote:
i.MX6SL EVK board has a 3*3 keypad matrix to support 8 keypads,
enable them, the keymap is as below:
SW6: 0x0067/* KEY_UP */
SW7: 0x0001006c/* KEY_DOWN
On Tue, Jan 14, 2014 at 04:29:50PM +0800, Shawn Guo wrote:
OK, I saw this define #define MATRIX_KEY(row, col, code)
in include/dt-bindings/input/input.h, please ignore my first
reply. Will do it in V2.
On Tue, Jan 14, 2014 at 03:37:09PM +0800, Anson Huang wrote:
i.MX6SL EVK board has a 3*3
*/
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6sl-evk.dts | 28
arch/arm/boot/dts/imx6sl.dtsi|2 ++
2 files changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index f5e4513
-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6sl-evk.dts | 28
arch/arm/boot/dts/imx6sl.dtsi|2 ++
2 files changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index f5e4513..f23b5d1 100644
On Tue, Jan 14, 2014 at 01:27:43PM +0400, Alexander Shiyan wrote:
Вторник, 14 января 2014, 17:23 +08:00 от Anson Huang b20...@freescale.com:
i.MX6SL EVK board has a 3*3 keypad matrix to support 8 keypads,
enable them, the keymap is as below:
SW6: MATRIX_KEY(0x0, 0x0, 0x67) /* ROW0
As some modules are common for all i.MX6 SOCs, to avoid
checking cpu type for drivers that needs them, just add a
new compatible name for them.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6sl.dtsi |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
i.MX6SL's suspend in ocram function is derived from i.MX6Q,
the only difference is the offset of DDR IO pins. It can
lower the DDR IO power from ~10mA@1.2V to ~1mA@1.2V,
measured on i.MX6SL EVK board, SH5.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/mach-imx/Makefile
i.MX6DL's suspend in ocram function is derived from i.MX6Q,
the only difference is the offset of DDR IO pins. It can
lower the DDR IO power from ~26mA@1.5V to ~15mA@1.5V,
measured on i.MX6Q/DL SabreSD board, R25.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/mach-imx/pm-imx6q.c
structure(imx6_cpu_pm_info)
low address ===
Signed-off-by: Anson Huang b20...@freescale.com
---
Changes since V3:
1. Add const to MMDC IO offset array;
2. Improve for-loop code to save code lines;
3. Use __aligned to save one variable
/* KEY_LEFT */
SW12: 0x0272/* KEY_VOLUMEDOWN */
SW13: 0x02010073/* KEY_VOLUMEUP */
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6sl-evk.dts | 27 +++
arch/arm/boot/dts/imx6sl.dtsi|2 ++
2 files changed, 29 insertions(+)
diff
IOMUXC node is included in i.mx6qdl.dtsi, so no need
to overwrite it, as it is a reused module from i.mx6q.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6dl.dtsi |4
1 file changed, 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot
structure(imx6_cpu_pm_info)
low address ===
Signed-off-by: Anson Huang b20...@freescale.com
---
Changes since V2:
1. save MMDC IO info during initialization for once, no
need to do save everytime before suspend;
2. Improve ocram suspend
i.MX6DL's suspend in ocram function is derived from i.MX6Q,
the only difference is the offset of DDR IO pins. It can
lower the DDR IO power from ~26mA@1.5V to ~15mA@1.5V,
measured on i.MX6Q/DL SabreSD board, R25.
Signed-off-by: Anson Huang b20...@freescale.com
---
Changes since V2:
Only do
i.MX6SL's suspend in ocram function is derived from i.MX6Q,
the only difference is the offset of DDR IO pins. It can
lower the DDR IO power from ~10mA@1.2V to ~1mA@1.2V,
measured on i.MX6SL EVK board, SH5.
Signed-off-by: Anson Huang b20...@freescale.com
---
Changes since V2:
Do necessary
.
Signed-off-by: Anson Huang b20...@freescale.com
---
.../devicetree/bindings/thermal/imx-thermal.txt|4
drivers/thermal/imx_thermal.c | 20
2 files changed, 24 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/imx
.
Signed-off-by: Anson Huang b20...@freescale.com
---
.../devicetree/bindings/thermal/imx-thermal.txt|2 ++
drivers/thermal/imx_thermal.c | 18 ++
2 files changed, 20 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt
.
Signed-off-by: Anson Huang b20...@freescale.com
---
.../devicetree/bindings/thermal/imx-thermal.txt|4
drivers/thermal/imx_thermal.c | 18 ++
2 files changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/imx
On Wed, Dec 18, 2013 at 03:05:39PM +0800, Shawn Guo wrote:
On Tue, Dec 17, 2013 at 05:08:21PM -0500, Anson Huang wrote:
i.MX6Q needs to update vddarm, vddsoc/pu regulators when cpu freq
is changed, each setpoint has different voltage, so we need to
pass vddarm, vddsoc/pu's freq-voltage info
is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang b20...@freescale.com
---
drivers/cpufreq/imx6q
i.MX6Q needs to update vddarm, vddsoc/pu regulators when cpu freq
is changed, each setpoint has different voltage, so we need to
pass vddarm, vddsoc/pu's freq-voltage info from dts together.
Signed-off-by: Anson Huang b20...@freescale.com
---
.../devicetree/bindings/cpufreq/cpufreq-imx6.txt
i.MX6Q needs to update vddarm, vddsoc/pu regulators when cpu freq
is changed, each setpoint has different voltage, so we need to
pass vddarm, vddsoc/pu's freq-voltage info from dts together.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6q.dtsi |7 +++
1 file
This patch adds cpufreq dts for i.mx6dl to support cpufreq driver.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6dl.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index
This patch adds support for imx6qdl-sabresd board's power
key, the key is named SW1 on board, press it can wake up
system from suspend.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6qdl-sabresd.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch
.
Signed-off-by: Anson Huang b20...@freescale.com
---
drivers/thermal/imx_thermal.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 1d6c801..7abbc04 100644
--- a/drivers/thermal/imx_thermal.c
+++ b
thermal sensor needs dedicated clock to work in correct way,
so we need to add necessary clock info in dts.
Signed-off-by: Anson Huang b20...@freescale.com
---
.../devicetree/bindings/thermal/imx-thermal.txt|2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree
Thermal sensor needs pll3_usb_otg when measuring temperature,
so we need to pass clk info to thermal driver.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6qdl.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot
is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang b20...@freescale.com
---
drivers/cpufreq/imx6q
i.MX6Q needs to update vddarm, vddsoc/pu regulators when cpu freq
is changed, each setpoint has different voltage, so we need to
pass vddarm, vddsoc/pu's freq-voltage info from dts together.
Signed-off-by: Anson Huang b20...@freescale.com
---
.../devicetree/bindings/cpufreq/cpufreq-imx6.txt
65 matches
Mail list logo
