Re: [PATCH v2 1/2] usb: dwc2: optionally assert phy "full reset" when waking up

Rob, On Mon, Nov 2, 2015 at 8:12 AM, Rob Herring <robh...@kernel.org> wrote: > On Fri, Oct 30, 2015 at 3:17 PM, Douglas Anderson <diand...@chromium.org> > wrote: >> From: Doug Anderson <diand...@chromium.org> >> >> On the rk3288 USB host-only port (

Re: [PATCH v2 1/2] usb: dwc2: optionally assert phy "full reset" when waking up

Hi, On Mon, Nov 2, 2015 at 9:16 AM, Rob Herring <robh...@kernel.org> wrote: > On Mon, Nov 2, 2015 at 10:22 AM, Doug Anderson <diand...@chromium.org> wrote: >> Rob, >> >> On Mon, Nov 2, 2015 at 8:12 AM, Rob Herring <robh...@kernel.org> wrote: >>> O

Re: [REPOST PATCH 0/3] dwc2 patches to allow wakeup on Rockchip rk3288

John, On Mon, Oct 26, 2015 at 7:05 PM, John Youn <john.y...@synopsys.com> wrote: > On 10/21/2015 9:23 AM, Doug Anderson wrote: >> John, >> >> On Mon, Jul 6, 2015 at 11:27 AM, Douglas Anderson <diand...@chromium.org> >> wrote: >>>

Re: [PATCH 0/4] Patches to fix remote wakeup on rk3288 dwc2 "host" port

Rob, On Mon, Oct 26, 2015 at 4:05 PM, Rob Herring wrote: >>> A DT reset controller seems like a bit of an overkill here. I think this >>> would be much more simple if we just add a phy reset hook to the phy >>> subsystem. >> >> Adding a reset hook in the PHY subsystem does seem

Re: [PATCH 0/4] Patches to fix remote wakeup on rk3288 dwc2 "host" port

Hi, On Mon, Oct 26, 2015 at 4:49 PM, Doug Anderson <diand...@chromium.org> wrote: > One note: the "full" PHY reset is actually not in the register map of > the PHY. It is amazingly enough in the CRU (clock reset unit). So if > we actually exposed the "full&qu

Re: [PATCH 0/4] Patches to fix remote wakeup on rk3288 dwc2 "host" port

Rob, On Sat, Oct 24, 2015 at 11:10 AM, Rob Herring wrote: > On 10/23/2015 01:28 PM, Douglas Anderson wrote: >> The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288 >> has a hardware errata that causes everything to get confused when we get >> a remote wakeup.

Re: [PATCH v4 3/3] ARM: dts: rockchip: Add the OTP gpio pinctrl

Hi, On Fri, Oct 23, 2015 at 4:25 AM, Caesar Wang wrote: > Add the "init" anf "sleep" pinctrl as the OTP gpio state. > We need the OTP pin is gpio state before resetting the TSADC controller, > since the tshut polarity will generate a high signal. > > "init" pinctrl property

Re: [PATCH v1 2/2] ARM: dts: rockchip: Add the OTP gpio pinctrl

Caesar, On Tue, Oct 20, 2015 at 9:42 PM, Caesar Wang wrote: > I think the description is right, maybe need other decriptions. > The tshut polarity is low in a short period of time when the TSADC > controller is reset. > > In other words, > > If T < (setting temperature),

Re: [REPOST PATCH 0/3] dwc2 patches to allow wakeup on Rockchip rk3288

John, On Mon, Jul 6, 2015 at 11:27 AM, Douglas Anderson wrote: > This series of patches, together with > from Chris Zhong and a > dts change allow us to wake up from a USB device on rk3288 boards. > The patches were tested on

Re: [RESEND PATCH v2 1/2] dt-bindings: rockchip-thermal: Add the "init" pinctrl in this document

Caesar, On Wed, Oct 21, 2015 at 7:30 PM, Caesar Wang wrote: > The "init" pinctrl is defined we'll set > pinctrl to this state before probe and then "default" after probe. > > Add the "init" pinctrl as the OTP gpio state, since we need switch > the pin to gpio state before

Re: [PATCH v1 1/2] dt-bindings: Sync the dts to this document

Hi, On Tue, Oct 20, 2015 at 7:42 PM, Caesar Wang wrote: > Add the OTP gpio state, we need switch the pin to gpio state > before the TSADC controller is reset. > > Signed-off-by: Caesar Wang > --- > > Changes in v1: > - As the Doug comments, add the

Re: [PATCH v1 2/2] ARM: dts: rockchip: Add the OTP gpio pinctrl

Caesar, On Tue, Oct 20, 2015 at 7:43 PM, Caesar Wang wrote: > We need the OTP pin is gpio state before resetting the TSADC controller, > since the tshut polarity will generate a high signal. It might or might not be "high" depending on polarity, right? It's just possible

Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support

Hi, On Mon, Oct 19, 2015 at 3:11 AM, Anand Moon wrote: > 1 Drop the cd-gpios changes. pinctrl-0 changes. Right. > 2 Fix the regulator changes for vmmc/vqmmc with disable of > regulator-always-on; I'm not totally sure I understand. You should need to keep vmmc and

Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support

Hi, On Tue, Oct 13, 2015 at 6:06 PM, Alim Akhtar wrote: > +Doug > Hello, > AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50 > and SDR104 modes. > > [1]: http://www.spinics.net/lists/linux-mmc/msg28186.html > > What I remember is, one need to set

Re: [PATCH] ARM: dts: Add Exynos5250 Snow Rev5+ support

Hi, On Wed, Sep 30, 2015 at 4:44 PM, Krzysztof Kozlowski wrote: >> Switching the default meaning of "google,snow" to Rev5 is probably not >> something we'd ever want to do, since it could confuse "rev3" boards >> (which should be serviced by the rev4 dts). From comments

Re: [PATCH] ARM: dts: Add Exynos5250 Snow Rev5+ support

Hi, On Tue, Sep 29, 2015 at 5:30 PM, Krzysztof Kozlowski wrote: > Now the exynos5250-snow.dts means in fact Rev4... but there is no > information in DTS about it. I think adding compatible > "google,snow-rev4" makes sense: > 1. For informational purposes (this could be

Re: [PATCH] ARM: dts: Add Exynos5250 Snow Rev5+ support

Javier, On Tue, Sep 29, 2015 at 4:57 AM, Javier Martinez Canillas wrote: > There are 2 revisions of the Exynos5250 Snow Chromebook that were shipped: > Rev4 and Rev5. The only difference between these 2 revisions is the codec, > Rev4 has a max98095 codec while Rev5 has a

Re: [PATCH] ARM: dts: Add ddc i2c reference to veyron

Hi, On Thu, Sep 3, 2015 at 8:18 AM, Russell King - ARM Linux wrote: > On Thu, Sep 03, 2015 at 09:46:38AM -0500, Rob Herring wrote: >> Yes, that is fairly common (ADV75xx is same), and we would not >> describe an I2C bus in DT in that case. Same with HPD directly handled

Re: [PATCH] ARM: dts: Add ddc i2c reference to veyron

Hi, On Thu, Sep 3, 2015 at 8:46 AM, Rob Herring wrote: > On Thu, Sep 3, 2015 at 10:18 AM, Russell King - ARM Linux > wrote: >> On Thu, Sep 03, 2015 at 09:46:38AM -0500, Rob Herring wrote: >>> Yes, that is fairly common (ADV75xx is same), and we

Re: [PATCH] ARM: dts: Add ddc i2c reference to veyron

Lucas, On Thu, Sep 3, 2015 at 9:13 AM, Lucas Stach wrote: >> 6. Once you start using the dw_hdmi's i2c block with the currently >> posted patch against mainline (to do this you not only need the patch >> but you need to remove the ddc-i2c-bus property, set the pinmux, and

Re: [PATCH] ARM: dts: Add ddc i2c reference to veyron

Hi, On Wed, Sep 2, 2015 at 2:25 PM, Douglas Anderson wrote: > The ddc-i2c-bus property was missing from the veyron dtsi file since > downstream the ddc-i2c-bus was still being specified in rk3288.dtsi and > nobody noticed when the veyron dtsi was sent upstream. Add it. >

Re: [PATCH] ARM: dts: Add ddc i2c reference to veyron

Rob, On Wed, Sep 2, 2015 at 5:13 PM, Rob Herring wrote: > On Wed, Sep 2, 2015 at 4:25 PM, Douglas Anderson > wrote: >> The ddc-i2c-bus property was missing from the veyron dtsi file since >> downstream the ddc-i2c-bus was still being specified in

Re: [PATCH v2 1/2] ARM: dts: rockchip: pull up cts lines on rk3288

Alex, On Wed, Sep 2, 2015 at 4:27 PM, Alexandru M Stan wrote: > The flow control lines from a user accessible UART are optional, > the user might not have anything connected to those pins. > In order to prevent random interrupts happening and noise affecting > the cts pin

Re: [PATCH v2 2/2] ARM: dts: rockchip: Remove specific cts pullup from veyron

Alex, On Wed, Sep 2, 2015 at 4:27 PM, Alexandru M Stan wrote: > With the previous patch ("rk3288: pull up cts lines") this is redundant, > I sent that patch for the same reason this existed here, so the lines don't > wiggle randomly when disconnected. > > Signed-off-by:

Re: [PATCH] ARM: dts: rk3288: pull up cts lines

Alex, On Wed, Sep 2, 2015 at 3:20 PM, Alexandru M Stan wrote: > The flow control lines from a user accessible UART are optional, > the user might not have anything connected to those pins. > In order to prevent random interrupts happening and noise affecting > that pin it

Re: [RESEND PATCH v16 4/4] ARM: dts: add the support power-domain node on RK3288 SoCs

Mike, On Fri, Aug 28, 2015 at 1:02 PM, Michael Turquette mturque...@linaro.org wrote: Hi Doug, Quoting Doug Anderson (2015-08-27 19:03:20) Kevin, On Thu, Aug 27, 2015 at 5:24 PM, Kevin Hilman khil...@kernel.org wrote: That is not really workable: the attach and detach happen in probe

Re: [PATCH 2/2] ARM: dts: rockchip: correct regulator PM properties

Hi, On Tue, Aug 18, 2015 at 11:19 PM, Heiko Stuebner he...@sntech.de wrote: great, just take into account the deep vs. shallow suspend modes :-) One note: do you think it would make sense to re-implement shallow suspend as standby? I had a proof of concept doing that in

Re: [PATCH v3] ARM: dts: rockchip: add veyron-jaq board

Brian, On Mon, Aug 24, 2015 at 3:58 PM, Brian Norris briannor...@chromium.org wrote: a.k.a. Haier Chromebook 11, and others Signed-off-by: Brian Norris briannor...@chromium.org Cc: Alexandru M Stan ams...@chromium.org Cc: Douglas Anderson diand...@chromium.org Reviewed-by: Javier Martinez

Re: [RESEND PATCH v16 4/4] ARM: dts: add the support power-domain node on RK3288 SoCs

Kevin, On Thu, Aug 27, 2015 at 5:24 PM, Kevin Hilman khil...@kernel.org wrote: That is not really workable: the attach and detach happen in probe/remove path; if you do not have driver for the device you will miss the clocks for it. And in my proposal, I suggested that clocks without drivers

Re: [RESEND PATCH v16 4/4] ARM: dts: add the support power-domain node on RK3288 SoCs

Kevin, On Tue, Aug 25, 2015 at 3:45 PM, Kevin Hilman khil...@kernel.org wrote: To put things in a concrete way, for pd_vio we'd go through the entire device tree ourselves and find all properties that look like power-domains = power RK3288_PD_VIO;. We'd then find the parent of those

Re: [RESEND PATCH v16 4/4] ARM: dts: add the support power-domain node on RK3288 SoCs

Kevin, On Tue, Aug 25, 2015 at 2:07 PM, Kevin Hilman khil...@kernel.org wrote: Caesar Wang w...@rock-chips.com writes: We can add more domains node in the future. This patch add the needed clocks into power-controller. As the discuess about all the device clocks being listed in the

Re: [RFC PATCH v5 1/9] mmc: dw_mmc: Add external dma interface support

Heiko, On Fri, Aug 14, 2015 at 3:13 PM, Heiko Stübner he...@sntech.de wrote: Hi Shawn, Am Freitag, 14. August 2015, 16:34:35 schrieb Shawn Lin: DesignWare MMC Controller can supports two types of DMA mode: external dma and internal dma. We get a RK312x platform integrated dw_mmc and ARM

Re: [PATCH v1 2/3] Documentation: dt-bindings: add dt binding info for dwc2 reset control

lyz, On Tue, Aug 11, 2015 at 12:56 AM, Yunzhi Li l...@rock-chips.com wrote: Signed-off-by: Yunzhi Li l...@rock-chips.com --- Documentation/devicetree/bindings/usb/dwc2.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt

Re: [PATCH 2/2] ARM: dts: rockchip: Add veyron-speedy board

Hi, On Tue, Jul 21, 2015 at 10:44 PM, Romain Perier romain.per...@gmail.com wrote: Which is formally known as The Asus C201 chromebook Signed-off-by: Romain Perier romain.per...@gmail.com --- Documentation/devicetree/bindings/arm/rockchip.txt | 10 +- arch/arm/boot/dts/Makefile

Re: [PATCH 0/3] dwc2 patches to allow wakeup on Rockchip rk3288

Felipe, On Mon, Jul 6, 2015 at 10:48 AM, Felipe Balbi ba...@ti.com wrote: On Mon, Jun 22, 2015 at 04:52:21PM -0700, Douglas Anderson wrote: This series of patches, together with https://patchwork.kernel.org/patch/6652341/ from Chris Zhong and a dts change allow us to wake up from a USB device

Re: [PATCH 2/3] Documentation: dt-bindings: Add snps,need-phy-for-wake for dwc2 USB

Rob, On Tue, Jun 23, 2015 at 7:17 AM, Rob Herring robherri...@gmail.com wrote: On Mon, Jun 22, 2015 at 6:52 PM, Douglas Anderson diand...@chromium.org wrote: Some SoCs with a dwc2 USB controller may need to keep the PHY on to support remote wakeup. Allow specifying this as a device tree

Re: [RESEND PATCH] ARM: dts: cros-ec-keyboard: Add support for some Japanese keys

Hi, On Tue, May 5, 2015 at 6:03 PM, Chris Zhong z...@rock-chips.com wrote: Add support for 4 Japanese keys Signed-off-by: Chris Zhong z...@rock-chips.com Reviewed-by: Doug Anderson diand...@chromium.org --- arch/arm/boot/dts/cros-ec-keyboard.dtsi | 4 1 file changed, 4 insertions

Re: [PATCH] ARM: dts: rockchip: Add dmac_bus rx and tx for uart2

Hi, On Tue, Jun 16, 2015 at 4:37 AM, Heiko Stuebner he...@sntech.de wrote: Just for the record and if anybody is interested to work in this, we have an issue with the dma implementation [0] that is not yet solved upstream. From what I've remember, that mostly got triggered on higher speeds,

Re: [PATCH] ARM: socfpga: dts: Add a ciu clock node for sdmmc

Hi, On Fri, Apr 10, 2015 at 1:56 PM, dingu...@opensource.altera.com wrote: From: Dinh Nguyen dingu...@opensource.altera.com The CIU(Card Interface Unit) clock is used by the dw_mmc IP to clock an SD card. The ciu_clk is the sdmmc_clk passed through a fixed divider of 4. This patch adds

Re: [PATCH] arm: dts: rk3288: Enable Cortex-A12 HW PMU events

with Rockchip: these numbers don't actually match the TRM, but apparently the TRM is wrong. Since these numbers work and the numbers came from Rockchip: Reviewed-by: Doug Anderson diand...@chromium.org -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message

Re: [PATCH 1/2] spi/rockchip: Round up clock rate divisor to err on the safe side

. Signed-off-by: Julius Werner jwer...@chromium.org --- drivers/spi/spi-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Doug Anderson diand...@chromium.org -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord

Re: [PATCH 2/2] spi/rockchip: Add device tree property to configure Rx Sample Delay

jwer...@chromium.org --- .../devicetree/bindings/spi/spi-rockchip.txt| 4 drivers/spi/spi-rockchip.c | 21 + 2 files changed, 25 insertions(+) Reviewed-by: Doug Anderson diand...@chromium.org -- To unsubscribe from this list: send

Re: [PATCH v3 3/3] ARM: dts: Specify VMMC and VQMMC on rk3288-evb

Heiko, On Tue, Jan 6, 2015 at 9:44 AM, Heiko Stübner he...@sntech.de wrote: Hi Doug, Am Montag, 15. Dezember 2014, 16:22:20 schrieb Doug Anderson: Specifying these rails should eventually let us do UHS. Signed-off-by: Doug Anderson diand...@chromium.org --- Changes in v3: None Changes

[PATCH v4 4/4] ARM: dts: Specify VMMC and VQMMC on rk3288-evb

Specifying these rails should eventually let us do UHS. Signed-off-by: Doug Anderson diand...@chromium.org --- Changes in v4: - Add vcc_sd regulator which is present on EVB 2.0 boards Changes in v3: None Changes in v2: - Fix subject line arch/arm/boot/dts/rk3288-evb.dtsi | 23

Re: [PATCH 5/6] ASoC: samsung: Extend Snow driver to support max98089

Andreas, On Thu, Feb 19, 2015 at 9:56 AM, Andreas Färber afaer...@suse.de wrote: Am 19.02.2015 um 18:44 schrieb Doug Anderson: On Thu, Feb 19, 2015 at 1:44 AM, Mark Brown broo...@kernel.org wrote: On Wed, Feb 18, 2015 at 07:25:58PM +0100, Andreas Färber wrote: static const struct

Re: [PATCH] mmc: dw_mmc: fix bug that cause mmc_test failture

Addy, Your subject needs work. It should at least touch on what the bug was. Please use a subject more like: mmc: dw_mmc: fix mmc_test by not sending abort for DRTO / EBE errors On Mon, Jan 26, 2015 at 4:04 AM, Addy Ke addy...@rock-chips.com wrote: The STOP command can terminate a data

Re: [PATCH 5/6] ASoC: samsung: Extend Snow driver to support max98089

Mark, On Thu, Feb 19, 2015 at 1:44 AM, Mark Brown broo...@kernel.org wrote: On Wed, Feb 18, 2015 at 07:25:58PM +0100, Andreas Färber wrote: static const struct of_device_id snow_of_match[] = { + { .compatible = google,snow-audio-max98089, }, { .compatible =

Re: [PATCH 1/6] ASoC: max98088: Document DT bindings

Andreas, On Thu, Feb 19, 2015 at 6:13 AM, Andreas Färber afaer...@suse.de wrote: I see that a master clock (mclk) is added in patch 6/6 but the max98088 codec driver does handle this clock. If the SoC XCLKOUT provides the master clock to the max98089 codec in Spring like is the case for the

Re: [PATCH 1/2] mmc: core: use card pointer as the first parameter of execute_tuning()

Ulf, On Tue, Jan 27, 2015 at 7:18 AM, Ulf Hansson ulf.hans...@linaro.org wrote: I asked Addy to post upstream against mmc_send_tuning(), but I guess he didn't (he posted against Alex's NAKed patch instead). ...when I talked to him about it, Addy was asserting that when tuning fails it is

Re: [PATCH 1/2] mmc: core: use card pointer as the first parameter of execute_tuning()

Ulf, On Mon, Jan 26, 2015 at 7:15 AM, Ulf Hansson ulf.hans...@linaro.org wrote: On 26 January 2015 at 12:19, Addy Ke addy...@rock-chips.com wrote: We need to take the card pointer in execute_tuning() for mmc_send_status(), mmc_send_status() is an mmc core function, not intended for host's to

Re: [PATCH v3 1/4] mmc: dw_mmc: exynos: incorporate ciu_div into timing property

Alim, On Sun, Jan 4, 2015 at 2:43 PM, Alim Akhtar alim.akh...@gmail.com wrote: You are breaking backward compatibility here. If your change is merged then all old boards will instantly break. Since the dts and code changes will likely be merged through different trees you'll end up with a

Re: [PATCH v3 1/4] mmc: dw_mmc: exynos: incorporate ciu_div into timing property

Alim, On Tue, Dec 30, 2014 at 10:43 PM, Alim Akhtar alim.akh...@samsung.com wrote: From: Seungwon Jeon tgih@samsung.com ciu_div may not be common value for all speed mode. So, it needs to be attached to CLKSEL timing. The more time I've spent looking at all of this stuff the less I like

[PATCH v3] i2c: rk3x: Account for repeated start time requirement

is incredibly likely. Signed-off-by: Doug Anderson diand...@chromium.org --- Note: This is based on Addy's patch (i2c: rk3x: fix bug that cause measured high_ns doesn't meet I2C specification) that can be found at https://patchwork.kernel.org/patch/5475331/. Changes in v3: - Totally changed code

Re: [PATCH] i2c: rk3x: Account for repeated start time requirement

Hi, On Thu, Dec 11, 2014 at 11:18 AM, Doug Anderson diand...@chromium.org wrote: On Rockchip I2C the controller drops SDA low in the repeated start condition at half the SCL high time. If we want to meet timing requirements, that means we need to hold SCL high for (4.7us * 2) when we're

Re: [PATCH 1/2] CHROMIUM: clk: rockchip: add clock IDs for the PVTM clocks

--- Note that I left a hole at 122 for SCLK_USBPHY480M_SRC which is floating around. I'm sure Heiko can adjust when he lands. include/dt-bindings/clock/rk3288-cru.h | 3 +++ 1 file changed, 3 insertions(+) Thanks for sending! Reviewed-by: Doug Anderson diand...@chromium.org

Re: [PATCH 2/2] CHROMIUM: clk: rockchip: add PVTM clocks on rk3288

...@chromium.org --- drivers/clk/rockchip/clk-rk3288.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Thanks for sending! Reviewed-by: Doug Anderson diand...@chromium.org -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord

Re: [PATCH 1/2] clk: rockchip: add clock ID for usbphy480m_src

that Heiko can fixup, this looks good to me. Reviewed-by: Doug Anderson diand...@chromium.org -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

Re: [PATCH v7 2/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY

power at suspend time. Tested-by: Doug Anderson diand...@chromium.org -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

Re: [PATCH v7 4/5] ARM: dts: rockchip: add rk3288 usb PHY

-pinky (on a 3.14 tree with backports), I can confirm that this properly gets us into low power at suspend time. Tested-by: Doug Anderson diand...@chromium.org This looks reasonable to me: Reviewed-by: Doug Anderson diand...@chromium.org -- To unsubscribe from this list: send the line

Re: [PATCH v7 5/5] ARM: dts: rockchip: Enable usb PHY on rk3288-evb board

. This does look reasonable to me, though: Reviewed-by: Doug Anderson diand...@chromium.org -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

[PATCH v2 3/3] ARM: dts: Specify VMMC and VQMMC on rk3288-evb

Specifying these rails should eventually let us do UHS. Signed-off-by: Doug Anderson diand...@chromium.org --- Changes in v2: - Fix subject line arch/arm/boot/dts/rk3288-evb.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288

[PATCH v3 3/3] ARM: dts: Specify VMMC and VQMMC on rk3288-evb

Specifying these rails should eventually let us do UHS. Signed-off-by: Doug Anderson diand...@chromium.org --- Changes in v3: None Changes in v2: - Fix subject line arch/arm/boot/dts/rk3288-evb.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch

Re: [PATCH v7 2/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY

Hi, On Fri, Dec 12, 2014 at 11:24 PM, Kishon Vijay Abraham I kis...@ti.com wrote: hi, On Saturday 13 December 2014 05:49 AM, Doug Anderson wrote: Yunzhi, On Fri, Dec 12, 2014 at 7:07 AM, Yunzhi Li l...@rock-chips.com wrote: This patch to add a generic PHY driver for ROCKCHIP usb PHYs

Re: [PATCH v7 2/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY

Yunzhi, On Fri, Dec 12, 2014 at 7:07 AM, Yunzhi Li l...@rock-chips.com wrote: This patch to add a generic PHY driver for ROCKCHIP usb PHYs, currently this driver can support RK3288. The RK3288 SoC have three independent USB PHY IPs which are all configured through a set of registers located

Re: [PATCH v6 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY

Yunzhi, On Thu, Dec 11, 2014 at 1:55 AM, Yunzhi Li l...@rock-chips.com wrote: + rk_phy-clk = of_clk_get(child, 0); + if (IS_ERR(rk_phy-clk)) { + dev_warn(dev, failed to get clock\n); + rk_phy-clk = NULL; +

Re: [PATCH v6 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY

Kishon, On Thu, Dec 11, 2014 at 2:27 AM, Kishon Vijay Abraham I kis...@ti.com wrote: I didn't mean that. You can get rid of this entire xlate stuff if you use something like below phy@xxx { compatible = ; phy1:usb_phy { } phy2:usb_phy { }; };

Re: [PATCH v6 2/5] Documentation: bindings: add dt documentation for Rockchip usb PHY

Yunzhi, On Thu, Dec 11, 2014 at 1:55 AM, Yunzhi Li l...@rock-chips.com wrote: This patch adds a binding that describes the Rockchip usb PHYs found on Rockchip SoCs usb interface. Technically the bindings patch is supposed to come before the driver. So this should be patch #1 and the driver

Re: [PATCH v6 2/5] Documentation: bindings: add dt documentation for Rockchip usb PHY

Hi, On Thu, Dec 11, 2014 at 10:46 AM, Doug Anderson diand...@chromium.org wrote: Yunzhi, On Thu, Dec 11, 2014 at 1:55 AM, Yunzhi Li l...@rock-chips.com wrote: This patch adds a binding that describes the Rockchip usb PHYs found on Rockchip SoCs usb interface. Technically the bindings patch

Re: [PATCH] i2c: rk3x: Account for repeated start time requirement

Hi, On Thu, Dec 11, 2014 at 11:18 AM, Doug Anderson diand...@chromium.org wrote: - min_low_ns = spec_min_low_ns + fall_ns; - min_high_ns = spec_min_high_ns + rise_ns; + /* +* For repeated start we need at least (spec_setup_start * 2) to meet +* (tSU;SDA

Re: [PATCH v2 1/2] mfd: dt-bindings: add the description about dvs gpio for rk808

, voltage changes will happen + without being very quickly with no slow ramp time. Remove the words without being I assume Mark would rather make that change himself instead of getting a respin, so probably don't send out a new version unless other changes are needed. Reviewed-by: Doug Anderson

[PATCH v2] i2c: rk3x: Account for repeated start time requirement

to be the same as the SCL falling time, which is incredibly likely. Signed-off-by: Doug Anderson diand...@chromium.org --- Note: This is based on Addy's patch (i2c: rk3x: fix bug that cause measured high_ns doesn't meet I2C specification) that can be found at https://patchwork.kernel.org/patch/5475331

Re: [PATCH v6 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY

Yunzhi, On Thu, Dec 11, 2014 at 10:09 AM, Doug Anderson diand...@chromium.org wrote: + rk_phy-phy = devm_phy_create(dev, NULL, ops); This has the wrong number of arguments. Even before the change that added the 4th argument, this is still wrong because ops is supposed

[PATCH] ARM: dts: Bump SD card pin drive strength up on rk3288-evb

strength (maybe because there are two physical SD card slots hooked up to the same pin?). Fix the problem by bumping up the drive strength of the sdmmc lines. Signed-off-by: Doug Anderson diand...@chromium.org Fixes: 536f6b91d21b (mmc: dw_mmc: Reset DMA before enabling IDMAC) --- arch/arm/boot/dts

[PATCH 4/4] ARK: dts: Specify VMMC and VQMMC on rk3288-evb

Specifying these rails should eventually let us do UHS. Signed-off-by: Doug Anderson diand...@chromium.org --- arch/arm/boot/dts/rk3288-evb.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 6194d67..1956a23

[PATCH] i2c: designware: Fix falling time bindings doc

this is a typo because: * The source code includes the -ns * The example in the bindings includes the -ns. Fix the typo. Signed-off-by: Doug Anderson diand...@chromium.org Fixes: 6468276b2206 (i2c: designware: make SCL and SDA falling time configurable) --- Documentation/devicetree/bindings/i2c/i2c

Re: [PATCH] ARM: dts: rockchip: set dw_mmc max-freq 150Mhz

is also listed in the latest datasheet. It's unfortunate that we won't get full speed of SDR104 or hs200 on this SoC, but correctness certainly outweighs performance. Reviewed-by: Doug Anderson diand...@chromium.org I have tested that this prevents the speed from going above 150MHz on rk3288-pinky

Re: [PATCH v2] mmc: dw_mmc: add quirk for broken data transfer over scheme

Addy, On Mon, Dec 1, 2014 at 11:50 PM, addy ke addy...@rock-chips.com wrote: We don't know why we have this problem, but this problem is really exist, and we need patch to fix this problem now. I will post a follow up change when we find the root cause. To me that seems reasonable. Certainly

Re: [PATCH 2/2] ASoC: rockchip: i2s: add support for grabbing output clock to codec

Jianqun, This ought to be a v3 patch and ideally ought to describe differences from v2 (after the cut). Please have Kever or Chris review your next patch before sending it out since I think they are familiar with the process. On Tue, Dec 2, 2014 at 6:52 AM, Jianqun Xu jay...@rock-chips.com

Re: [PATCH 1/2] ASoC: rockchip-i2s: dt: add an optional property i2s_clk_out

reasonable to me. Reviewed-by: Doug Anderson diand...@chromium.org -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

Re: [PATCH v3] mmc: dw_mmc: add quirk for broken data transfer over scheme

-by: Doug Anderson diand...@chromium.org -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

Re: [PATCH 2/2] ASoC: rockchip: i2s: add support for grabbing output clock to codec

On Tue, Dec 2, 2014 at 5:03 PM, Jianqun x...@rock-chips.com wrote: Hi Doug: 在 12/03/2014 01:54 AM, Doug Anderson 写道: Jianqun, This ought to be a v3 patch and ideally ought to describe differences from v2 (after the cut). Please have Kever or Chris review your next patch before sending

Re: [PATCH v10 0/4] This suspend patch is only support cut off the power of cpu and some external

Hi, On Mon, Dec 1, 2014 at 11:51 AM, Kevin Hilman khil...@kernel.org wrote: Chris Zhong z...@rock-chips.com writes: devices, since we still lack power_domain driver, so the other power rail of rk3288 need keep power on. I have tested it on rk3288-evb board, atop next-20141112. goto suspend

Re: [PATCH v10 4/4] ARM: dts: rockchip: add suspend settings for rk3288-evb-rk808

patch. I did confirm that if I hacked the wakeup source to be just from GPIOs that it stayed asleep and could be awakened by the power button. I tested on linux-next with evb-rk808. Reviewed-by: Doug Anderson diand...@chromium.org Tested-by: Doug Anderson diand...@chromium.org -Doug

Re: [PATCH v10 0/4] This suspend patch is only support cut off the power of cpu and some external

Hi, On Mon, Dec 1, 2014 at 2:08 PM, Doug Anderson diand...@chromium.org wrote: Hi, On Mon, Dec 1, 2014 at 11:51 AM, Kevin Hilman khil...@kernel.org wrote: Chris Zhong z...@rock-chips.com writes: devices, since we still lack power_domain driver, so the other power rail of rk3288 need keep

Re: [PATCH v9 3/4] ARM: dts: add RK3288 suspend support

this in the board DTS file since some boards need it. Signed-off-by: Tony Xie x...@rock-chips.com Signed-off-by: Chris Zhong z...@rock-chips.com Reviewed-by: Doug Anderson diand...@chromium.org Tested-by: Doug Anderson diand...@chromium.org --- Changes in v9: None This is untrue. v8 had more

Re: [PATCH v4] clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers

Yingjoe, On Wed, Nov 26, 2014 at 6:41 AM, Yingjoe Chen yingjoe.c...@mediatek.com wrote: Sorry for the (very) late reply. I just realize today MT8135 need this and the other patch [1] to boot SMP correctly. I've applied both patches and they works fine. Thanks :) Excellent. It's helpful to

Re: [PATCH v2] mmc: dw_mmc: add quirk for broken data transfer over scheme

Hi, On Tue, Nov 25, 2014 at 12:10 AM, Addy Ke addy...@rock-chips.com wrote: This patch add a new quirk to add a s/w timer to notify the driver to terminate current transfer and report a data timeout to the core, if DTO interrupt does NOT come within the given time. dw_mmc call

Re: [PATCH v9 4/4] ARM: dts: rockchip: add suspend settings for rk3288-evb-rk808

Chris, On Mon, Nov 24, 2014 at 11:32 PM, Chris Zhong z...@rock-chips.com wrote: vcc_ddr: DCDC_REG3 { regulator-always-on; regulator-boot-on; regulator-name = vcc_ddr; +

Re: [PATCH v3 0/2] Add support for the rockchip mmc clock phases using the framework

Heiko, On Tue, Nov 25, 2014 at 1:35 AM, Heiko Stübner he...@sntech.de wrote: Am Dienstag, 18. November 2014, 13:08:26 schrieb Alexandru M Stan: For now all I have is the getter and setter for the phase, nothing that uses it (that is ready). You can test the getter like this: localhost ~ # cat

Re: [PATCH 0/2] Increase the maximum cpu frequency of rk3288

Hi, On Tue, Nov 25, 2014 at 8:23 AM, Heiko Stübner he...@sntech.de wrote: Hi Chris, Kever, Am Mittwoch, 26. November 2014, 00:13:40 schrieb Kever Yang: On 11/25/2014 05:37 PM, Chris Zhong wrote: The maximum cpu frequency of rk3288 can up to 1.8Ghz, but the vdd_cpu need set to 1.4v. I've

[PATCH 1/2] clk: rockchip: add binding ID for DMC (memory controller) clocks on rk3288

From: Jeff Chen c...@rock-chips.com The DMC clocks need to be turned off at runtime, so we should have IDs so we can export them. Signed-off-by: Jeff Chen c...@rock-chips.com [dianders: split into two patches; adjusted commit msg] Signed-off-by: Doug Anderson diand...@chromium.org --- include

Re: [PATCH 1/2] clk: rockchip: add binding ID for DMC (memory controller) clocks on rk3288

Heiko, On Tue, Nov 25, 2014 at 4:45 PM, Heiko Stübner he...@sntech.de wrote: Am Dienstag, 25. November 2014, 16:13:02 schrieb Doug Anderson: From: Jeff Chen c...@rock-chips.com The DMC clocks need to be turned off at runtime, so we should have IDs so we can export them. Signed-off-by: Jeff

Re: [PATCH] mmc: dw_mmc: try pick the exact same voltage as vmmc for vqmmc

Ulf, On Mon, Nov 24, 2014 at 5:29 AM, Ulf Hansson ulf.hans...@linaro.org wrote: 2. Several people I've talked to have expressed concerns that our minimum value is 2.7V. Apparently that's really on the edge and makes EEs a little nervous. The quick sample of cards sitting on my desk shows

Re: [PATCH] mmc: dw_mmc: try pick the exact same voltage as vmmc for vqmmc

Addy, On Mon, Nov 24, 2014 at 6:38 PM, Addy addy...@rock-chips.com wrote: In worst case scenario, VDD = 3.6V and VIO = 2.7V. That gives as the factor of 0.75, thus we are inside spec but without margins. * From eMMC4.5 spec: 1. (VDDF)vcc: Supply voltage for flash memory, which is 2.7v --

Re: [PATCH] mmc: dw_mmc: try pick the exact same voltage as vmmc for vqmmc

Ulf, On Fri, Nov 21, 2014 at 4:06 AM, Ulf Hansson ulf.hans...@linaro.org wrote: [...] Sure If the first card is sd2.0 since startup, dw_mci_switch_voltage will not be called, That can't be right. mmc_power_up() should trigger dw_mci_switch_voltage() to be invoked. Hmmm, I think you're

Re: [PATCH] mmc: dw_mmc: try pick the exact same voltage as vmmc for vqmmc

Hi, On Fri, Nov 21, 2014 at 9:42 AM, Doug Anderson diand...@chromium.org wrote: Ulf, On Fri, Nov 21, 2014 at 4:06 AM, Ulf Hansson ulf.hans...@linaro.org wrote: [...] Sure If the first card is sd2.0 since startup, dw_mci_switch_voltage will not be called, That can't be right

Re: [PATCH v4] clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers

Daniel, On Wed, Oct 8, 2014 at 12:33 AM, Sonny Rao sonny...@chromium.org wrote: From: Doug Anderson diand...@chromium.org Some 32-bit (ARMv7) systems are architected like this: * The firmware doesn't know and doesn't care about hypervisor mode and we don't want to add the complexity

Re: [PATCH 1/2] clk: rockchip: add bindings for the mmc clock phases

Hi, On Fri, Nov 14, 2014 at 2:52 PM, Alexandru M Stan ams...@chromium.org wrote: This will be used in a later patch for clock phase tuning. Suggested-by: Heiko Stuebner he...@sntech.de Signed-off-by: Alexandru M Stan ams...@chromium.org --- include/dt-bindings/clock/rk3288-cru.h | 10

Re: [PATCH] ARM: dts: fix PWM clock found on RK3288 Socs

Caesar, On Tue, Nov 18, 2014 at 7:25 PM, Caesar Wang caesar.w...@rock-chips.com wrote: We use the new PWM IP on RK3288,but the PWM's clock indeed incorrect. Signed-off-by: Caesar Wang caesar.w...@rock-chips.com --- arch/arm/boot/dts/rk3288.dtsi | 8 1 file changed, 4

Re: [PATCH v11 2/3] power-domain: rockchip: add power doamin driver

Hi, On Wed, Nov 12, 2014 at 2:01 PM, Caesar Wang caesar.w...@rock-chips.com wrote: In order to meet high performance and low power requirements, a power management unit is designed or saving power when RK3288 in low power mode. The RK3288 PMU is dedicated for managing the power ot the whole

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