On 06/04/2015 10:26 AM, Dinh Nguyen wrote:
On 06/04/2015 09:28 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits
On 03/09/2015 03:02 PM, Andy Shevchenko wrote:
On Mon, Mar 9, 2015 at 9:47 PM, Thor Thayer
ttha...@opensource.altera.com wrote:
On 03/09/2015 01:54 PM, Andy Shevchenko wrote:
Yes, I just need the 32 bit write. I was trying to remain consistent but I
agree that only changing only writes
On 03/10/2015 03:44 PM, Andy Shevchenko wrote:
On Tue, Mar 10, 2015 at 10:34 PM, Thor Thayer
ttha...@opensource.altera.com wrote:
On 03/09/2015 03:02 PM, Andy Shevchenko wrote:
On Mon, Mar 9, 2015 at 9:47 PM, Thor Thayer
ttha...@opensource.altera.com wrote:
On 03/09/2015 01:54 PM, Andy
On 03/07/2015 01:52 PM, Andy Shevchenko wrote:
On Sat, Mar 7, 2015 at 1:46 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Altera's Arria10 SoC interconnect requires a 32 bit write for APB
peripherals. The current spi-dw driver uses 16bit accesses
On 03/07/2015 01:58 PM, Andy Shevchenko wrote:
On Sat, Mar 7, 2015 at 1:46 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Altera's Arria10 architecture requires a 32bit write accesses for
APB peripherals. The current spi-dw driver uses 16bit
On 03/09/2015 01:19 PM, Mark Brown wrote:
On Mon, Mar 09, 2015 at 01:11:28PM -0500, Thor Thayer wrote:
I stay away from dashes because these variable names are problematic to
parse in languages like Python which may be used as an external tool.
Dashes are idiomatic for device tree
On 03/09/2015 01:54 PM, Andy Shevchenko wrote:
On Mon, Mar 9, 2015 at 8:01 PM, Thor Thayer
ttha...@opensource.altera.com wrote:
On 03/07/2015 01:52 PM, Andy Shevchenko wrote:
On Sat, Mar 7, 2015 at 1:46 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha
On 03/05/2015 03:54 PM, Andy Shevchenko wrote:
On Thu, 2015-03-05 at 14:41 -0600, Thor Thayer wrote:
Hi Andy,
On 03/05/2015 04:43 AM, Andy Shevchenko wrote:
On Wed, 2015-03-04 at 16:01 -0600, Thor Thayer wrote:
Hi Andy,
On 03/04/2015 02:44 PM, Andy Shevchenko wrote:
On Wed, 2015-03-04
Hi Andy,
On 03/05/2015 04:43 AM, Andy Shevchenko wrote:
On Wed, 2015-03-04 at 16:01 -0600, Thor Thayer wrote:
Hi Andy,
On 03/04/2015 02:44 PM, Andy Shevchenko wrote:
On Wed, 2015-03-04 at 14:31 -0600, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Hi Andy,
On 03/04/2015 02:44 PM, Andy Shevchenko wrote:
On Wed, 2015-03-04 at 14:31 -0600, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
The Altera Arria10 SoC requires 32 bit accesses to peripherals. The
DesignWare SPI peripheral registers are on 32bit
Hi Andy,
On 03/04/2015 02:55 PM, Andy Shevchenko wrote:
On Wed, 2015-03-04 at 14:31 -0600, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Altera's Arria10 SoC requires a 32 bit access for peripherals.
The current spi-dw driver uses 16bit accesses in some
Hi Mark,
On 02/06/2015 12:45 PM, Mark Rutland wrote:
On Fri, Jan 09, 2015 at 02:53:53AM +, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for On-Chip RAM on machine
startup. The ECC has to be enabled before data
Hi Mark
On 02/06/2015 01:24 PM, Mark Rutland wrote:
On Fri, Jan 09, 2015 at 02:53:56AM +, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch
On 02/06/2015 01:17 PM, Mark Rutland wrote:
On Fri, Jan 09, 2015 at 02:53:55AM +, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller
Hi Device Tree Maintainers,
On 01/08/2015 08:53 PM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare
Hi Device Tree Maintainers,
On 01/08/2015 08:53 PM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process
On 12/26/2014 01:40 PM, Rob Herring wrote:
On Tue, Dec 23, 2014 at 10:34 AM, Thor Thayer
ttha...@opensource.altera.com wrote:
Hi,
What is the best way to queue devicetree child nodes so the node is passed
in the platform_device pointer to the probe() function?
Documentation/devicetree/usage
Hi,
What is the best way to queue devicetree child nodes so the node is
passed in the platform_device pointer to the probe() function?
Documentation/devicetree/usage-model.txt has the following:
For Linux DT support, the generic behaviour is for child devices to be
registered by the
On 12/02/2014 09:01 AM, Mark Rutland wrote:
Hi Thor,
On Mon, Dec 01, 2014 at 08:47:41PM +, Thor Thayer wrote:
Hi Boris,
On 11/18/2014 02:56 PM, Thor Thayer wrote:
Hi all,
On 11/11/2014 06:14 PM, ttha...@opensource.altera.com wrote:
From: Thor Thayerttha...@opensource.altera.com
On 12/02/2014 09:11 AM, Mark Rutland wrote:
On Wed, Nov 12, 2014 at 12:14:20AM +, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for On-Chip RAM on machine
startup. The ECC has to be enabled before data is
is stored
+};
+
+#endif /* #ifdef CONFIG_EDAC_ALTERA_L2C */
+
MODULE_LICENSE(GPL v2);
MODULE_AUTHOR(Thor Thayer);
-MODULE_DESCRIPTION(EDAC Driver for Altera SDRAM Controller);
+MODULE_DESCRIPTION(EDAC Driver for Altera Memories);
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe
On 12/02/2014 08:57 AM, Mark Rutland wrote:
On Wed, Nov 12, 2014 at 12:14:23AM +, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies
Hi Boris,
On 11/18/2014 02:56 PM, Thor Thayer wrote:
Hi all,
On 11/11/2014 06:14 PM, ttha...@opensource.altera.com wrote:
From: Thor Thayerttha...@opensource.altera.com
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies
Hi all,
On 11/11/2014 06:14 PM, ttha...@opensource.altera.com wrote:
From: Thor Thayerttha...@opensource.altera.com
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM
Hi Dinh,
On 11/07/2014 02:13 PM, Dinh Nguyen wrote:
Hi Thor,
On 11/07/2014 10:54 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for L2 cache on machine
startup. The ECC has to be enabled before data is
is stored in memory
Hi Dinh,
On 11/07/2014 02:32 PM, Dinh Nguyen wrote:
Hi Thor,
On 11/07/2014 10:54 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for On-Chip RAM on machine
startup. The ECC has to be enabled before data is
is stored
Hi Boris!
On 11/04/2014 09:12 AM, Borislav Petkov wrote:
On Thu, Oct 30, 2014 at 10:32:10AM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
Hi Borislav,
On 10/17/2014 03:33 PM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process in the platform
On 10/27/2014 03:43 PM, Borislav Petkov wrote:
On Mon, Oct 27, 2014 at 01:50:24PM -0500, Thor Thayer wrote:
Do you have any comments about this driver?
Just a question: why do you have three .c files for something which
does only error injection and nothing else AFAICT? Why isn't this part
On 10/27/2014 04:59 PM, Borislav Petkov wrote:
On Mon, Oct 27, 2014 at 04:35:00PM -0500, Thor Thayer wrote:
Should I move the EDAC Device probe and error handling from
altera_edac_mgr.c to altera_edac.c? Can I mix the MC and Device models
in the same file?
Right, for basic practical reasons
On 10/17/2014 01:52 AM, Steffen Trumtrar wrote:
Hi!
On Thu, Oct 16, 2014 at 05:07:31PM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Add 2 SPI nodes to SOCFPGA device tree.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Remove
On 10/17/2014 09:27 AM, Mark Brown wrote:
On Fri, Oct 17, 2014 at 08:55:21AM -0500, Thor Thayer wrote:
I didn't see it documented in the dw-spi bindings but I did see a reference
to .bus_num in the static structure (spi_board_info) shown in
spi-summary.txt. If the bus-num isn't defined
On 10/08/2014 03:05 PM, Mark Brown wrote:
On Wed, Oct 08, 2014 at 02:27:08PM -0500, ttha...@opensource.altera.com wrote:
+ spidev@0 {
+ compatible = spidev;
+ reg = 0;/* chip select */
+
On 10/07/2014 06:12 PM, Mark Brown wrote:
On Tue, Oct 07, 2014 at 02:48:17PM -0500,ttha...@opensource.altera.com wrote:
Add 2 SPI nodes to SOCFPGA device tree. Update copyright.
Update spi-dw.txt with bus-num as an optional property.
Again, this is just randomly mixing multiple changes.
On 10/08/2014 03:01 AM, Steffen Trumtrar wrote:
Hi!
On Tue, Oct 07, 2014 at 03:55:54PM -0500, Thor Thayer wrote:
On 10/07/2014 03:31 PM, Steffen Trumtrar wrote:
Hi!
On Tue, Oct 07, 2014 at 02:48:17PM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha
On 10/08/2014 03:17 AM, Andy Shevchenko wrote:
On Tue, 2014-10-07 at 14:48 -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
1. The of_node element must be initialized to enable discovery of node
children. The discovery takes place
On 10/04/2014 11:18 PM, Masami Hiramatsu wrote:
(2014/10/04 6:42), Dinh Nguyen wrote:
On 10/03/2014 04:51 AM, Masami Hiramatsu wrote:
Hi Dinh,
(2014/10/02 20:38), Dinh Nguyen wrote:
On 10/1/14, 5:18 PM, Thor Thayer wrote:
On 10/01/2014 04:10 PM, Dinh Nguyen wrote:
On 10/1/14, 4:07 PM
On 10/07/2014 03:31 PM, Steffen Trumtrar wrote:
Hi!
On Tue, Oct 07, 2014 at 02:48:17PM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Add 2 SPI nodes to SOCFPGA device tree. Update copyright.
Update spi-dw.txt with bus-num as an optional property
On 10/07/2014 03:40 PM, Mark Brown wrote:
On Tue, Oct 07, 2014 at 02:48:16PM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
1. The of_node element must be initialized to enable discovery of node
children. The discovery takes place
On 10/04/2014 11:21 PM, Masami Hiramatsu wrote:
(2014/10/02 1:31), ttha...@opensource.altera.com wrote:
+void socfpga_init_ocram_ecc(void)
+{
+struct device_node *np;
+const __be32 *prop;
+u32 ocr_edac_addr, iram_addr, len;
+void __iomem *mapped_ocr_edac_addr;
+size_t
On 10/02/2014 05:58 AM, Mark Rutland wrote:
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
@@ -0,0 +1,15 @@
+Altera SoCFPGA L2 cache Error Detection and Correction [EDAC]
+
+Required Properties:
+- compatible : Should be altr,l2-edac
That string looks too generic.
On 10/02/2014 06:38 AM, Dinh Nguyen wrote:
On 10/1/14, 5:18 PM, Thor Thayer wrote:
On 10/01/2014 04:10 PM, Dinh Nguyen wrote:
On 10/1/14, 4:07 PM, Thor Thayer wrote:
On 10/01/2014 12:13 PM, Dinh Nguyen wrote:
On 10/1/14, 11:31 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer
On 10/01/2014 11:45 AM, Dinh Nguyen wrote:
On 10/1/14, 11:31 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Adding the device tree entries needed to support the Altera L2
cache and OCRAM EDAC.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
On 10/01/2014 11:53 AM, Mark Rutland wrote:
On Wed, Oct 01, 2014 at 05:31:31PM +0100, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC_DEVICE framework. The EDAC
manager
On 10/01/2014 12:13 PM, Dinh Nguyen wrote:
On 10/1/14, 11:31 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for L2 cache and OCRAM on machine
startup. In both cases, the ECC has to be enabled before data
is stored in memory
On 10/01/2014 04:10 PM, Dinh Nguyen wrote:
On 10/1/14, 4:07 PM, Thor Thayer wrote:
On 10/01/2014 12:13 PM, Dinh Nguyen wrote:
On 10/1/14, 11:31 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
[...]
static void socfpga_cyclone5_restart(enum
On 08/14/2014 01:49 PM, Pavel Machek wrote:
On Mon 2014-08-11 10:18:13, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
Signed-off-by: Thor Thayer ttha
On 08/14/2014 01:49 PM, Pavel Machek wrote:
On Mon 2014-08-11 10:18:12, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.
Signed-off
On 08/15/2014 11:07 AM, atull wrote:
On Fri, 15 Aug 2014, Steffen Trumtrar wrote:
Hi!
Hello
Thanks for the feedback...
ttha...@opensource.altera.com writes:
From: Thor Thayer ttha...@opensource.altera.com
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
On 08/02/2014 12:08 PM, Steffen Trumtrar wrote:
Hi!
On Fri, Aug 01, 2014 at 05:27:57PM -0500, Thor Thayer wrote:
On 08/01/2014 03:13 AM, Lee Jones wrote:
On Thu, 31 Jul 2014, Thor Thayer wrote:
On 07/31/2014 03:26 AM, Lee Jones wrote:
On Wed, 30 Jul 2014, ttha...@opensource.altera.com
On 08/01/2014 03:13 AM, Lee Jones wrote:
On Thu, 31 Jul 2014, Thor Thayer wrote:
On 07/31/2014 03:26 AM, Lee Jones wrote:
On Wed, 30 Jul 2014, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Add a simple MFD for the Altera SDRAM Controller.
Signed-off
On 07/31/2014 03:26 AM, Lee Jones wrote:
On Wed, 30 Jul 2014, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Add a simple MFD for the Altera SDRAM Controller.
Signed-off-by: Alan Tull at...@opensource.altera.com
Signed-off-by: Thor Thayer ttha
On Thu, Jun 26, 2014 at 4:45 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Wed, Jun 25, 2014 at 10:15:26PM +0100, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
Signed-off-by: Thor
Hi Mark
On Thu, Jun 26, 2014 at 4:45 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Wed, Jun 25, 2014 at 10:15:26PM +0100, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
Signed-off
Hi Dinh,
On Wed, Jun 25, 2014 at 4:12 PM, Dinh Nguyen dinh.li...@gmail.com wrote:
Hi Thor,
On 06/25/2014 04:15 PM, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic
On Sat, Jun 21, 2014 at 4:06 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
On Fri, Jun 20, 2014 at 06:22:02PM -0500, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM EDAC bindings and device tree changes
v2: Changes to SoC EDAC source code
On Mon, May 26, 2014 at 4:57 AM, Borislav Petkov b...@alien8.de wrote:
On Thu, May 15, 2014 at 11:04:51AM -0500, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To Cc list
On Tue, May 27, 2014 at 2:11 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
On Wed, May 21, 2014 at 10:38:34AM -0500, Thor Thayer wrote:
On Tue, May 20, 2014 at 9:44 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
Hi!
On Tue, May 20, 2014 at 09:31:06AM -0500, Alan Tull wrote
On Tue, May 20, 2014 at 9:44 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
Hi!
On Tue, May 20, 2014 at 09:31:06AM -0500, Alan Tull wrote:
On Mon, May 19, 2014 at 2:37 PM, Thor Thayer tthayer.li...@gmail.com wrote:
diff --git
a/Documentation/devicetree/bindings/arm/altera
On Fri, May 16, 2014 at 2:53 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
Hi!
On Thu, May 15, 2014 at 11:04:49AM -0500, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project
On Mon, May 19, 2014 at 2:12 PM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
Hi Thor!
On Mon, May 19, 2014 at 01:36:30PM -0500, Thor Thayer wrote:
On Fri, May 16, 2014 at 2:53 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
Hi!
On Thu, May 15, 2014 at 11:04:49AM -0500, ttha
On Mon, May 12, 2014 at 7:12 PM, Borislav Petkov b...@alien8.de wrote:
On Mon, May 12, 2014 at 06:36:57PM -0500, ttha...@altera.com wrote:
+ ptemp[0] = 0x5A5A5A5A;
+ ptemp[1] = 0xA5A5A5A5;
+ /* Clear the error injection bits */
+ regmap_write(drvdata-mc_vbase, CTLCFG,
On Fri, May 9, 2014 at 3:52 PM, Borislav Petkov b...@alien8.de wrote:
On Fri, May 09, 2014 at 03:31:53PM -0500, Thor Thayer wrote:
Yes, good point. Our hardware can't recover from Double Bit Errors so
I'll go back to the panic() in that path. I like the flexibility of
the command line
On Thu, May 8, 2014 at 5:44 PM, Dinh Nguyen dinh.li...@gmail.com wrote:
On 5/5/14 5:52 PM, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To Cc list. Add maintainer
On Fri, May 9, 2014 at 8:52 AM, Borislav Petkov b...@alien8.de wrote:
On Thu, May 08, 2014 at 03:37:19PM -0500, Thor Thayer wrote:
Yes. Their reasoning is that they want to retain the rights and
warranty language with the file (just in case the COPYING file
changes).
Ok, thanks for checking
On Thu, May 8, 2014 at 7:05 AM, Borislav Petkov b...@alien8.de wrote:
On Mon, May 05, 2014 at 05:52:17PM -0500, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
Missing commit message.
Whoops. I don't know what happened there. I'll fix it.
---
v2: Use the SDRAM controller
Hi Sören
On Mon, May 5, 2014 at 6:16 PM, Sören Brinkmann
soren.brinkm...@xilinx.com wrote:
Hi Thor,
On Mon, 2014-05-05 at 05:52PM -0500, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM controller bindings and device
tree changes
On Tue, May 6, 2014 at 10:42 AM, Dinh Nguyen dingu...@altera.com wrote:
On Mon, 2014-05-05 at 17:52 -0500, Thor Thayer wrote:
From: Thor Thayer ttha...@altera.com
---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To Cc list. Add
On Wed, 2014-04-23 at 16:54 +0200, Borislav Petkov wrote:
On Tue, Apr 15, 2014 at 06:30:10PM -0500, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers
On Mon, 2014-04-21 at 12:27 +0200, Pavel Machek wrote:
Hi!
From: Thor Thayer ttha...@altera.com
Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers are used by the FPGA bridge so
these are accessed through
On Tue, 2014-04-08 at 13:52 -0500, Rob Herring wrote:
On Tue, Apr 8, 2014 at 11:02 AM, delicious quinoa
delicious.qui...@gmail.com wrote:
On Tue, Apr 8, 2014 at 9:33 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote:
On Tue
On Tue, 2014-04-08 at 13:52 -0500, Rob Herring wrote:
On Tue, Apr 8, 2014 at 11:02 AM, delicious quinoa
delicious.qui...@gmail.com wrote:
On Tue, Apr 8, 2014 at 9:33 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote:
On Tue
On Tue, 2014-04-08 at 13:52 -0500, Rob Herring wrote:
On Tue, Apr 8, 2014 at 11:02 AM, delicious quinoa
delicious.qui...@gmail.com wrote:
On Tue, Apr 8, 2014 at 9:33 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote:
On Tue
On Tue, 2014-04-08 at 12:08 +0200, Borislav Petkov wrote:
On Mon, Apr 07, 2014 at 04:54:09PM -0500, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers
On Tue, 2014-04-08 at 14:45 +0200, Steffen Trumtrar wrote:
On Tue, Apr 08, 2014 at 11:45:25AM +0100, Mark Rutland wrote:
On Mon, Apr 07, 2014 at 10:54:09PM +0100, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
Added EDAC support for reporting ECC errors of CycloneV
On Tue, 2014-04-08 at 15:38 +0200, Steffen Trumtrar wrote:
Hi!
On Mon, Apr 07, 2014 at 04:54:07PM -0500, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.
[snip
On Tue, 2014-04-08 at 18:22 +0200, Borislav Petkov wrote:
On Tue, Apr 08, 2014 at 05:10:54PM +0100, Mark Rutland wrote:
Typically the bindings would go with the driver via the appropriate
subsystem maintainer. That way we don't get bindings without drivers
or vice-versa if there's a problem
On Wed, 2014-04-02 at 00:19 +0200, Steffen Trumtrar wrote:
Hi!
On Tue, Apr 01, 2014 at 03:11:41PM -0500, Thor Thayer - Sendmail wrote:
On Tue, 2014-04-01 at 07:28 +0200, Steffen Trumtrar wrote:
Hi!
On Mon, Mar 31, 2014 at 05:07:06PM -0500, ttha...@altera.com wrote:
From: Thor
On Tue, 2014-04-01 at 07:33 +0200, Steffen Trumtrar wrote:
On Mon, Mar 31, 2014 at 05:07:07PM -0500, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
snip
Can't we get rid of all these global pointers instead of adding to them?
Yes. I will remove this file from
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