Hi Maxime
Thanks for reviewing.
Yes for sure, i will add additional board informations.
Patrice
On 02/27/2014 01:23 PM, Maxime Coquelin wrote:
Hi Patrice,
Could you add an overview documentation as it has been done for other
STi platforms?
See Documentation/arm/sti/stih416-overview.txt
Hi Patrice,
Could you add an overview documentation as it has been done for other
STi platforms?
See Documentation/arm/sti/stih416-overview.txt
Thanks,
Maxime
On 01/30/2014 03:55 PM, Patrice CHOTARD wrote:
From: Alexandre TORGUE alexandre.tor...@st.com
This patch adds support to STiD127
On 06/02/14 16:46, Arnd Bergmann wrote:
On Wednesday 05 February 2014, srinivas kandagatla wrote:
Currently l2cc bindings has few optional properties like.
- arm,data-latency
- arm,tag-latency
- arm,dirty-latency
- arm,filter-ranges
- interrupts :
- cache-id-part:
- wt-override:
These
On Wednesday 05 February 2014, srinivas kandagatla wrote:
Currently l2cc bindings has few optional properties like.
- arm,data-latency
- arm,tag-latency
- arm,dirty-latency
- arm,filter-ranges
- interrupts :
- cache-id-part:
- wt-override:
These does not include properties to set
Hi Arnd,
On 31/01/14 20:15, Arnd Bergmann wrote:
On Friday 31 January 2014, srinivas kandagatla wrote:
Sorry if I missed the initial review, but can you explain
why this is needed to start with?
On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set
the way-size explicit
On 01/31/2014 09:15 PM, Arnd Bergmann wrote:
On Friday 31 January 2014, srinivas kandagatla wrote:
Sorry if I missed the initial review, but can you explain
why this is needed to start with?
On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set
the way-size explicit here.
Hi Arnd,
On 30/01/14 18:39, Arnd Bergmann wrote:
Actually reading the code in this file shows that the L2 cache
initialization is the only nonstandard thing in there. We should
really find a way to get rid of the entire function.
I think this will get rid of lot of code left in board-dt.
On Friday 31 January 2014, srinivas kandagatla wrote:
Sorry if I missed the initial review, but can you explain
why this is needed to start with?
On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set
the way-size explicit here.
Unfortunately, we keep going back and
From: Alexandre TORGUE alexandre.tor...@st.com
This patch adds support to STiD127 SoC.
The main adaptation is the L2 cache way size compare to STiH41x SoCs.
Signed-off-by: alexandre torgue alexandre.tor...@st.com
Signed-off-by: Patrice Chotard patrice.chot...@st.com
---
On Thursday 30 January 2014, Patrice CHOTARD wrote:
From: Alexandre TORGUE alexandre.tor...@st.com
This patch adds support to STiD127 SoC.
The main adaptation is the L2 cache way size compare to STiH41x SoCs.
Signed-off-by: alexandre torgue alexandre.tor...@st.com
Signed-off-by: Patrice
On Thursday 30 January 2014, Arnd Bergmann wrote:
On Thursday 30 January 2014, Patrice CHOTARD wrote:
From: Alexandre TORGUE alexandre.tor...@st.com
This patch adds support to STiD127 SoC.
The main adaptation is the L2 cache way size compare to STiH41x SoCs.
Signed-off-by: alexandre
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