On Tue, Sep 30, 2014 at 11:56:24PM +0800, Chen-Yu Tsai wrote:
On Tue, Sep 30, 2014 at 11:40 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sat, Sep 27, 2014 at 04:49:49PM +0800, Chen-Yu Tsai wrote:
Currently sunxi_divs_clk_setup assumes the number of child clocks
to be the
On Sat, Sep 27, 2014 at 04:49:49PM +0800, Chen-Yu Tsai wrote:
Currently sunxi_divs_clk_setup assumes the number of child clocks
to be the same as the number of clock-output-names, and a maximum
of SUNXI_DIVS_MAX_QTY child clocks.
On sun6i, PLL6 only has 1 child clock, but the parent would be
On Tue, Sep 30, 2014 at 11:40 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sat, Sep 27, 2014 at 04:49:49PM +0800, Chen-Yu Tsai wrote:
Currently sunxi_divs_clk_setup assumes the number of child clocks
to be the same as the number of clock-output-names, and a maximum
of
Currently sunxi_divs_clk_setup assumes the number of child clocks
to be the same as the number of clock-output-names, and a maximum
of SUNXI_DIVS_MAX_QTY child clocks.
On sun6i, PLL6 only has 1 child clock, but the parent would be used
as well, thereby also having it's own clock-output-names
