On 09/10/15 14:47, Bharat Kumar Gogada wrote:
>> Hi Bharat,
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>>>
>>> +/* SSPL ERROR */ +#define SLVERR 0x02
>>> +#define DECERR
>>> 0x03 + +struct nwl_msi {/* struct nwl_msi - MSI
> Hi Bharat,
>> > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> >
> > +/* SSPL ERROR */
> > +#define SLVERR 0x02
> > +#define DECERR 0x03
> > +
> > +struct nwl_msi { /* struct nwl_msi - MSI inf
On 09/10/15 09:51, Bharat Kumar Gogada wrote:
>> On 09/10/15 06:11, Bharat Kumar Gogada wrote:
>> +struct nwl_msi { /* struct nwl_msi - MSI information
*/
>> + struct msi_controller chip; /* chip: MSI controller */
>
>> We're moving away from msi_controlle
> On 09/10/15 06:11, Bharat Kumar Gogada wrote:
> +struct nwl_msi { /* struct nwl_msi - MSI information
> >> */
> + struct msi_controller chip; /* chip: MSI controller */
> >>>
> We're moving away from msi_controller altogether, as the kernel now
> has all
On Friday 09 October 2015 09:10:17 Marc Zyngier wrote:
> > Please let me know whether we require a separate msi file as
> > suggested in your previous comments to separate MSI controller and
> > PCIE controller in two files, if we don't have separate node. If we
> > do not need a separate node do w
On 09/10/15 06:11, Bharat Kumar Gogada wrote:
+struct nwl_msi { /* struct nwl_msi - MSI information
>> */
+ struct msi_controller chip; /* chip: MSI controller */
>>>
We're moving away from msi_controller altogether, as the kernel now
has all the necessary
> >> +struct nwl_msi { /* struct nwl_msi - MSI information
> */
> >> + struct msi_controller chip; /* chip: MSI controller */
> >
> >> We're moving away from msi_controller altogether, as the kernel now
> >> has all the necessary infrastructure to do this properly.
> >
> > Our
On 06/10/15 17:27, Bharat Kumar Gogada wrote:
> Subject: Re: [PATCH v3] PCI: Xilinx-NWL-PCIe: Added support for Xilinx
> NWL PCIe Host Controller
[...]
>> +struct nwl_msi {/* struct nwl_msi - MSI information */
>> +struct msi_controller chip; /* ch
On 06/10/15 17:27, Bharat Kumar Gogada wrote:
> Subject: Re: [PATCH v3] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
[...]
Please use an email client that does proper quoting - I cannot see what
you are replying to. Or at least annotate your answers so that
Subject: Re: [PATCH v3] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe
Host Controller
Hi Bharat,
On 06/10/15 16:44, Bharat Kumar Gogada wrote:
> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>
> Signed-off-by: Bharat Kumar Gogada
> Signed-off-by: Ravi Kir
Hi Bharat,
On 06/10/15 16:44, Bharat Kumar Gogada wrote:
> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>
> Signed-off-by: Bharat Kumar Gogada
> Signed-off-by: Ravi Kiran Gummaluri
> ---
> Added interrupt-map, interrupt-map-mask properties
> ---
> .../devicetree/bindings/pci/xil
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada
Signed-off-by: Ravi Kiran Gummaluri
---
Added interrupt-map, interrupt-map-mask properties
---
.../devicetree/bindings/pci/xilinx-nwl-pcie.txt| 56 ++
drivers/pci/host/Kconfig
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