On Wed, Dec 12, 2012 at 04:37:50PM +, Andrew Murray wrote:
[...]
diff --git a/drivers/of/address.c b/drivers/of/address.c
[...]
+ start = of_get_property(node, ranges, rlen);
+ if (start == NULL)
+ return NULL;
+
+ end = start + rlen;
I'm currently rewriting
Hi,
This patchset adds initial support for the NVIDIA's new Tegra 114
SoC (T114) based on the ARM Cortex-A15 MP. It has the minimal support
to allow the kernel to boot up into shell console. This can be used as
a basis for adding other device drivers for this SoC. Currently there
are 2 evaluation
Add tegra_chip_id TEGRA114 0x35
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
arch/arm/mach-tegra/fuse.h |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index ff1383d..da78434 100644
--- a/arch/arm/mach-tegra/fuse.h
+++
Relocate functions by clock functionarities{RTC, TMR}. Also created
some new functions as helper.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
drivers/clocksource/tegra20_timer.c | 160 +++
1 file changed, 86 insertions(+), 74 deletions(-)
diff --git
Add platform enabler for ARM arch_timer(TSC). TSC is more fine grained
timer than TMR0. If it's available, it will be used for clock source
and sched_clock. Otherwise, TMR0 is used. In any case TMR0 is
necessary for clock event.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
Initial support for Tegra 114 SoC. This is expected to be included in
the board DTS files, Tegra 114 SoC based evaluation board family.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
arch/arm/boot/dts/tegra114.dtsi | 89 +++
1 file changed, 89
Add a new evaluation board, Dalmore for Tegra 114 family.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
arch/arm/boot/dts/Makefile |3 ++-
arch/arm/boot/dts/tegra114-dalmore.dts | 21 +
2 files changed, 23 insertions(+), 1 deletion(-)
create mode 100644
Add a new evaluation board, Pluto for Tegra 114 family.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
arch/arm/boot/dts/Makefile |3 ++-
arch/arm/boot/dts/tegra114-pluto.dts | 21 +
2 files changed, 23 insertions(+), 1 deletion(-)
create mode 100644
Add new Tegra 114 SoC support.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
arch/arm/mach-tegra/Kconfig | 10 +++
arch/arm/mach-tegra/Makefile|1 +
arch/arm/mach-tegra/board-dt-tegra114.c | 48 +++
arch/arm/mach-tegra/common.c
Use CLK_IGNORE_UNUSED for the Tegra 114 SoC to ensure
clk_disable_unused() is not called. Otherwise the system will die,
because the usecount of the clocks is incorrect. This patch will be
reverted once the Tegra 114 clocks are implemented.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
On 20/12/12 09:44, Hiroshi Doyu wrote:
Add platform enabler for ARM arch_timer(TSC). TSC is more fine grained
timer than TMR0. If it's available, it will be used for clock source
and sched_clock. Otherwise, TMR0 is used. In any case TMR0 is
necessary for clock event.
Signed-off-by: Hiroshi
On 20/12/12 09:44, Hiroshi Doyu wrote:
The method to detect the number of CPU cores on Cortex-A9 MPCore and
Cortex-A15 MPCore is different. On Cortex-A9 MPCore we can get this
information from the Snoop Control Unit(SCU). On Cortex-A15 MPCore we
have to read it from the system
Felipe Balbi ba...@ti.com wrote @ Thu, 20 Dec 2012 11:06:25 +0100:
...
@@ -149,7 +154,26 @@ done:
*/
static void __init tegra_smp_init_cpus(void)
{
- unsigned int i, ncores = scu_get_core_count(scu_base);
+ unsigned int i, cpu_id, ncores;
+ u32 l2ctlr;
+ phys_addr_t pa;
Marc Zyngier marc.zyng...@arm.com wrote @ Thu, 20 Dec 2012 12:17:08 +0100:
On 20/12/12 09:44, Hiroshi Doyu wrote:
The method to detect the number of CPU cores on Cortex-A9 MPCore and
Cortex-A15 MPCore is different. On Cortex-A9 MPCore we can get this
information from the Snoop Control
On 20/12/12 09:44, Hiroshi Doyu wrote:
Initial support for Tegra 114 SoC. This is expected to be included in
the board DTS files, Tegra 114 SoC based evaluation board family.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
You definitely need to add some cpu nodes here, or get someone to merge
On 20/12/12 11:26, Hiroshi Doyu wrote:
Marc Zyngier marc.zyng...@arm.com wrote @ Thu, 20 Dec 2012 12:17:08 +0100:
On 20/12/12 09:44, Hiroshi Doyu wrote:
The method to detect the number of CPU cores on Cortex-A9 MPCore and
Cortex-A15 MPCore is different. On Cortex-A9 MPCore we can get this
Marc Zyngier marc.zyng...@arm.com wrote @ Thu, 20 Dec 2012 12:01:15 +0100:
On 20/12/12 09:44, Hiroshi Doyu wrote:
Add platform enabler for ARM arch_timer(TSC). TSC is more fine grained
timer than TMR0. If it's available, it will be used for clock source
and sched_clock. Otherwise, TMR0 is
On 20/12/12 11:57, Hiroshi Doyu wrote:
Marc Zyngier marc.zyng...@arm.com wrote @ Thu, 20 Dec 2012 12:01:15 +0100:
On 20/12/12 09:44, Hiroshi Doyu wrote:
Add platform enabler for ARM arch_timer(TSC). TSC is more fine grained
timer than TMR0. If it's available, it will be used for clock source
+
+ /* CNTFRQ */
+ asm(mcr p15, 0, %0, c14, c0, 0\n : : r (freq));
+ asm(mrc p15, 0, %0, c14, c0, 0\n : =r (val));
+ BUG_ON(val != freq);
This is scary. CNTFRQ is only writable from secure mode, and will
explode in any other situation.
Also, writing to CNTFRQ doesn't change the
On 20/12/12 12:22, Peter De Schrijver wrote:
+
+ /* CNTFRQ */
+ asm(mcr p15, 0, %0, c14, c0, 0\n : : r (freq));
+ asm(mrc p15, 0, %0, c14, c0, 0\n : =r (val));
+ BUG_ON(val != freq);
This is scary. CNTFRQ is only writable from secure mode, and will
explode in any other situation.
Also,
On Thu, Dec 20, 2012 at 01:33:42PM +0100, Marc Zyngier wrote:
On 20/12/12 12:22, Peter De Schrijver wrote:
+
+ /* CNTFRQ */
+ asm(mcr p15, 0, %0, c14, c0, 0\n : : r (freq));
+ asm(mrc p15, 0, %0, c14, c0, 0\n : =r (val));
+ BUG_ON(val != freq);
This is scary.
On 20/12/12 12:55, Peter De Schrijver wrote:
On Thu, Dec 20, 2012 at 01:33:42PM +0100, Marc Zyngier wrote:
On 20/12/12 12:22, Peter De Schrijver wrote:
+
+ /* CNTFRQ */
+ asm(mcr p15, 0, %0, c14, c0, 0\n : : r (freq));
+ asm(mrc p15, 0, %0, c14, c0, 0\n : =r (val));
+
On 20/12/12 13:25, Hiroshi Doyu wrote:
Marc Zyngier marc.zyng...@arm.com wrote @ Thu, 20 Dec 2012 13:05:45 +0100:
On 20/12/12 11:57, Hiroshi Doyu wrote:
Marc Zyngier marc.zyng...@arm.com wrote @ Thu, 20 Dec 2012 12:01:15 +0100:
On 20/12/12 09:44, Hiroshi Doyu wrote:
Add platform enabler
On Wed, 2012-12-19 at 11:12 -0600, Jon Hunter wrote:
I am not sure if I have missed your pull request, but wanted to see if
you had or were going to send a pull request for the DT changes for
v3.8? I believe that the merge window ends this week.
Not yet sent. I was waiting on Dan's changes,
Vivek,
On Wed, Dec 19, 2012 at 9:51 PM, Vivek Gautam gautamvivek1...@gmail.com wrote:
Hi Doug,
On Thu, Dec 20, 2012 at 3:18 AM, Doug Anderson diand...@chromium.org wrote:
Vivek,
Since you're changing the name, I would have expected to see a removal
of the old enum type in this patch. I
On 20/12/12 14:42, Hiroshi Doyu wrote:
Marc Zyngier marc.zyng...@arm.com wrote @ Thu, 20 Dec 2012 14:32:21 +0100:
On 20/12/12 12:55, Peter De Schrijver wrote:
On Thu, Dec 20, 2012 at 01:33:42PM +0100, Marc Zyngier wrote:
On 20/12/12 12:22, Peter De Schrijver wrote:
+
+ /* CNTFRQ */
+
On 12/19/2012 03:24 PM, Pratik Patel wrote:
[snip]
Currently we use the CoreSight virtual bus to conveniently list
sysfs configuration attributes for all the registered CoreSight
devices.
For eg:
/sys/bus/coresight/devices/coresight-etm0/attribute
On 12/18/2012 01:19 PM, prat...@codeaurora.org wrote:
From: Pratik Patel prat...@codeaurora.org
This driver manages CoreSight ETB (Embedded Trace Buffer) which
acts as a circular buffer sink collecting generated trace data.
Signed-off-by: Pratik Patel prat...@codeaurora.org
---
On Wed, Dec 19, 2012 at 10:37 PM, Vivek Gautam
gautamvivek1...@gmail.com wrote:
On Thu, Dec 20, 2012 at 5:00 AM, Doug Anderson diand...@chromium.org wrote:
On Tue, Dec 18, 2012 at 6:43 AM, Vivek Gautam gautam.vi...@samsung.com
wrote:
+static void s5p_ehci_phy_enable(struct s5p_ehci_hcd
Hi,
On Thu, Dec 20, 2012 at 12:21:36PM +0100, Hiroshi Doyu wrote:
Felipe Balbi ba...@ti.com wrote @ Thu, 20 Dec 2012 11:06:25 +0100:
...
@@ -149,7 +154,26 @@ done:
*/
static void __init tegra_smp_init_cpus(void)
{
- unsigned int i, ncores = scu_get_core_count(scu_base);
+
Hi Doug,
On Thu, Dec 20, 2012 at 10:23 PM, Doug Anderson diand...@chromium.org wrote:
Vivek,
On Wed, Dec 19, 2012 at 9:51 PM, Vivek Gautam gautamvivek1...@gmail.com
wrote:
Hi Doug,
On Thu, Dec 20, 2012 at 3:18 AM, Doug Anderson diand...@chromium.org wrote:
Vivek,
Since you're changing
On Thu, Dec 20, 2012 at 11:46:13AM -0600, Jon Hunter wrote:
On 12/19/2012 03:24 PM, Pratik Patel wrote:
[snip]
Currently we use the CoreSight virtual bus to conveniently list
sysfs configuration attributes for all the registered CoreSight
devices.
For eg:
On Thu, Dec 20, 2012 at 11:49:03AM -0600, Jon Hunter wrote:
On 12/18/2012 01:19 PM, prat...@codeaurora.org wrote:
From: Pratik Patel prat...@codeaurora.org
This driver manages CoreSight ETB (Embedded Trace Buffer) which
acts as a circular buffer sink collecting generated trace data.
On 12/20/2012 12:41 PM, Bryan Wu wrote:
This patch adds support for Tegra30 Beaver board in upstream kernel.
I think these look fine. I can apply after the merge window closes.
___
devicetree-discuss mailing list
devicetree-discuss@lists.ozlabs.org
Hi Pratik,
On Thu, Dec 20, 2012 at 8:51 PM, Pratik Patel prat...@codeaurora.org wrote:
On Thu, Dec 20, 2012 at 11:46:13AM -0600, Jon Hunter wrote:
On 12/19/2012 03:24 PM, Pratik Patel wrote:
[snip]
Currently we use the CoreSight virtual bus to conveniently list
sysfs configuration
Some matrix keypad drivers can support different numbers of rows and
columns. Add a generic binding for these.
Also define properties for the repeat rate, to allow a sane baseline to
be set up for the driver.
Implementation note:
In order to implement this binding in the kernel, we will need to
On 12/20/2012 01:23 PM, Simon Glass wrote:
Some matrix keypad drivers can support different numbers of rows and
columns. Add a generic binding for these.
Oh, I thought num-rows/columns were already there!
Anyway, looks fine to me, so,
Reviewed-by: Stephen Warren swar...@nvidia.com
Hi Simon,
On Thu, Dec 20, 2012 at 12:23:58PM -0800, Simon Glass wrote:
For the key repeat feature, we need to set this after the input device
is registered. So we would need to add a matrix_keypad_setup_input() or
similar to be called by the driver after input_register_device(). I am
less
Hi Dmitry,
On Thu, Dec 20, 2012 at 1:13 PM, Dmitry Torokhov
dmitry.torok...@gmail.com wrote:
Hi Simon,
On Thu, Dec 20, 2012 at 12:23:58PM -0800, Simon Glass wrote:
For the key repeat feature, we need to set this after the input device
is registered. So we would need to add a
Hi,
On Fri, Nov 30, 2012 at 07:57:35PM +0100, Daniel Mack wrote:
On 30.11.2012 18:40, Tony Lindgren wrote:
* Andreas Fenkart andreas.fenk...@streamunlimited.com [121130 03:21]:
The alternative was to configure dat1 line as a GPIO, while
waiting for an IRQ. Then configuring it back as
Without functional clock the omap_hsmmc module can't forward
SDIO IRQs to the system. This patch reconfigures dat1 line
as a gpio while the fclk is off. And uses SDIO IRQ detection of
the module, while fclk is present.
Signed-off-by: Andreas Fenkart andreas.fenk...@streamunlimited.com
---
tegra114.dtsi has the folloiwng tsc entry. So can we consider that
if dts has this entry, CNTFRQ is not set, which implies it's in secure
mode. kernel should set it up by itself? Otherwise, skip this setup
and use it. For example:
tsc {
compatible =
On 12/20/2012 01:51 PM, Pratik Patel wrote:
On Thu, Dec 20, 2012 at 11:46:13AM -0600, Jon Hunter wrote:
On 12/19/2012 03:24 PM, Pratik Patel wrote:
[snip]
Currently we use the CoreSight virtual bus to conveniently list
sysfs configuration attributes for all the registered CoreSight
On Thu, Dec 20, 2012 at 04:54:38PM -0600, Jon Hunter wrote:
On 12/20/2012 01:51 PM, Pratik Patel wrote:
Ok, so are you referring to making CoreSight devices register
with AMBA bus instead of platform bus keeping everything else
intact?
Yes exactly. However, please note I am not saying
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