This series enables the use of the additional cores on Rockchip
Cortex-A9 SoCs.
To achieve this, add the scu, the needed sram and power-management-unit.
Tested on a rk3066a (dual core) by me and on a rk3188 (quad core)
by Ulrich Prinz.
(Note: rk3188 support in general needs additional upcoming
The pool is created thru devm_gen_pool_create, so the call to
gen_pool_destroy is not necessary.
Instead the sram-clock must be turned off again if it exists.
Signed-off-by: Heiko Stuebner he...@sntech.de
Tested-by: Ulrich Prinz ulrich.pr...@googlemail.com
---
drivers/misc/sram.c |3 ++-
1
Some SoCs need parts of their sram for special purposes. So while being part
of the periphal, it should not be part of the genpool controlling the sram.
Threfore add an option mmio-sram-reserved to keep arbitary portions of the
sram from being part of the pool.
Suggested-by: Rob Herring
This adds the device-node and config select to enable the
scu in all Rockchip Cortex-A9 SoCs.
Signed-off-by: Heiko Stuebner he...@sntech.de
Tested-by: Ulrich Prinz ulrich.pr...@googlemail.com
---
arch/arm/boot/dts/rk3066a.dtsi |5 +
arch/arm/mach-rockchip/Kconfig |1 +
2 files
The Rockchip SoCs need a special part of their sram for bringup
of additional cores. Therefore also add a reserved section when adding the
mmio-sram node to keep the sram driver from using this space.
Signed-off-by: Heiko Stuebner he...@sntech.de
Tested-by: Ulrich Prinz
The pmu is needed to bring up the cores during smp operations.
Therefore add a node and documentation for it.
Signed-off-by: Heiko Stuebner he...@sntech.de
Tested-by: Ulrich Prinz ulrich.pr...@googlemail.com
---
Documentation/devicetree/bindings/arm/rockchip/pmu.txt | 16
This adds the necessary smp-operations and startup code to use
additional cores on Rockchip SoCs.
We currently hog the power management unit in the smp code, as it is
necessary to control the power to the cpu core and nothing else is
currently using it, so a generic implementation can be done
Am Freitag, 5. Juli 2013, 14:55:40 schrieb Fabio Estevam:
On Fri, Jul 5, 2013 at 9:41 AM, Heiko Stübner he...@sntech.de wrote:
Some SoCs need parts of their sram for special purposes. So while being
part of the periphal, it should not be part of the genpool controlling
the sram
There exist variants of the timer IP with some modified properties.
Therefore add infrastructure to handle hardware-quirks in the driver.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
arch/x86/kernel/apb_timer.c |4 ++--
drivers/clocksource/dw_apb_timer.c|7 +--
The Rockchip rk3188 SoCs use a variant of the timer with some slight
modifications. This series implements them as quirks for the dw_apb_timer.
Tested on a rk3188 for the quirk handling and on a rk3066a to check that
nothing broke.
Heiko Stuebner (5):
clocksource: dw_apb_timer: infrastructure
There exists variants of the apb-timer that use slightly different
register positions. To accomodate this, add elements to the timer struct
to hold the actual register offsets.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/clocksource/dw_apb_timer.c | 83
This adds a quirk for IP variants containing two load_count and value
registers that are used to provide 64bit accuracy on 32bit systems.
The added accuracy is currently not used, the driver is only adapted to
handle the different register layout and make it work on affected devices.
Some timer variants have different mechanisms to clear a pending timer
interrupt. Therefore don't hardcode the reading of the eoi register to
clear them, but instead use the already existing eoi callback for this.
Signed-off-by: Ulrich Prinz ulrich.pr...@googlemail.com
---
From: Ulrich Prinz ulrich.pr...@googlemail.com
Some variants of SOCs using dw_apb_timer have inverted logic for the
bit that sets one-shot / periodic mode or free running timer. This
commit adds the new APBTMR_QUIRK_INVERSE_PERIODIC.
Signed-off-by: Ulrich Prinz ulrich.pr...@googlemail.com
---
The rk3188 uses a variant of the timer containing two registers for load_count
and current_values.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
.../bindings/arm/rockchip/rk3188-timer.txt | 20
drivers/clocksource/dw_apb_timer_of.c |6 ++
2
this patch should have had a
From: Ulrich Prinz ulrich.pr...@googlemail.com
sorry for the mistake
Am Samstag, 6. Juli 2013, 00:54:35 schrieb Heiko Stübner:
Some timer variants use an inverted setting to mask the timer interrupt.
Therefore add a quirk to handle these variants.
Signed-off
this patch should have had a
From: Ulrich Prinz ulrich.pr...@googlemail.com
sorry for the mistake
Am Samstag, 6. Juli 2013, 00:54:07 schrieb Heiko Stübner:
Some variants of the dw_apb_timer don't have an eoi register but instead
expect a one to be written to the int_status register at eoi
this patch should have had a
From: Ulrich Prinz ulrich.pr...@googlemail.com
sorry for the mistake
Am Samstag, 6. Juli 2013, 00:53:36 schrieb Heiko Stübner:
Some timer variants have different mechanisms to clear a pending timer
interrupt. Therefore don't hardcode the reading of the eoi
Hi Philipp,
Am Dienstag, 25. Juni 2013, 11:04:34 schrieb Philipp Zabel:
Hi Heiko,
Am Dienstag, den 25.06.2013, 10:46 +0200 schrieb Heiko Stübner:
The pool is created thru devm_gen_pool_create, so the call to
gen_pool_destroy is not necessary.
Instead the sram-clock must be turned off
Hi Philipp,
Am Dienstag, 25. Juni 2013, 12:17:05 schrieb Philipp Zabel:
Hi Heiko,
Am Dienstag, den 25.06.2013, 10:47 +0200 schrieb Heiko Stübner:
Some SoCs need parts of their sram for special purposes. So while being
part of the periphal, it should not be part of the genpool controlling
This small series changes the dw_wdt driver, so that it is usable on
machines using the common clock framework (needs the clk to be prepared)
and devicetree (needs a binding).
Heiko Stuebner (3):
watchdog: dw_wdt: convert to SIMPLE_DEV_PM_OPS
watchdog: dw_wdt: use clk_prepare_enable and
The dw_wdt only provides PM_SLEEP operations, so convert the driver
to use SIMPLE_DEV_PM_OPS instead of populating the struct manually.
This has the added effect of simplifying the CONFIG_PM ifdefs.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/watchdog/dw_wdt.c | 11 +++
1
The dw_wdt does not use any platform-specific data, so no new properties
need to be introduced. The dw-apb-wdt naming follows other designware
components in the kernel and is also written like this in documentation
describing the component.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
This is necessary to make the driver work with platforms using the
common clock framework.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/watchdog/dw_wdt.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/watchdog/dw_wdt.c
This series enables the use of the additional cores on Rockchip
Cortex-A9 SoCs.
To achieve this, add the scu, the needed sram and power-management-unit.
changes since v1:
- add reserved block feature for mmio-sram, to not use two logical
sram nodes
- the sram content is kept intact while the
The pool is created thru devm_gen_pool_create, so the call to
gen_pool_destroy is not necessary.
Instead the sram-clock must be turned off again if it exists.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/misc/sram.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
Some SoCs need parts of their sram for special purposes. So while being part
of the periphal, it should not be part of the genpool controlling the sram.
Threfore add an option mmio-sram-reserved to keep arbitary portions of the
sram from being part of the pool.
Suggested-by: Rob Herring
This adds the device-node and config select to enable the
scu in all Rockchip Cortex-A9 SoCs.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
arch/arm/boot/dts/rk3066a.dtsi |5 +
arch/arm/mach-rockchip/Kconfig |1 +
2 files changed, 6 insertions(+)
diff --git
The Rockchip SoCs need a special part of their sram for bringup
of additional cores. Therefore also add a reserved section when adding the
mmio-sram node to keep the sram driver from using this space.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
The pmu is needed to bring up the cores during smp operations.
Therefore add a node and documentation for it.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
Documentation/devicetree/bindings/arm/rockchip/pmu.txt | 16
arch/arm/boot/dts/rk3066a.dtsi |
This adds the necessary smp-operations and startup code to use
additional cores on Rockchip SoCs.
We currently hog the power management unit in the smp code, as it is
necessary to control the power to the cpu core and nothing else is
currently using it, so a generic implementation can be done
PULL_PIN_DEFAULT is meant for hardware completely hiding any pull
settings from the driver, so that it's really only possible to turn
the pull on or off, but it not being possible to determine any
pull settings from software.
Also the binding-documentation for the pull arguments did not match
the
As Stephen Warren pointed out, some pinconf bindings had deficits
either in documentation or in the whole thought process.
Therefore this series tries to fix these issues by improving
documentation and removing the real controversial bindings for now.
Of the changed pinconf bindings only the
As the binding for slew-rate is under discussion and seems to need
more tought it will get removed for now, so it doesn't get an offical
release.
Therefore remove it again from the only current user, tz1090.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
Currently the debounce time pinconfig option uses an unspecified
time units unit. As pinconfig options should use SI units and a
real unit is also necessary for generic dt bindings, change it
to usec. Currently no driver is using the generic pinconfig option
for this, so the unit change is safe to
Some options currently take arguments in unspecified driver-specific units.
As pointed out by Stephen Warren, driver specific values should not be part
of generic devicetree bindings describing the hardware.
Therefore remove the critical bindings again, before they become part of
an official
Hi Mike,
Am Montag, 17. Juni 2013, 04:58:24 schrieb Mike Turquette:
Devicetree binding for the basic clock divider, plus the setup function
to register the clock. Based on the existing fixed-clock binding.
Signed-off-by: Mike Turquette mturque...@linaro.org
---
Changes since v1:
* mask
Am Dienstag, 18. Juni 2013, 02:53:59 schrieb Heiko Stübner:
Am Montag, 17. Juni 2013, 04:58:23 schrieb Mike Turquette:
Device Tree binding for the basic clock multiplexer, plus the setup
function to register the clock. Based on the existing fixed-clock
binding.
Includes minor
Fifth version of basic Rockchip A9 support.
Following a comment from Arnd, I stripped the submission from all specific
clocks, only using dummy clocks for now. It's enough to reach a shell in an
initramfs. MMC patches are currently pending on the mmc list, so if they also
get merged accessing the
This adds a basic clock setup for rk3066a SoCs, currently only using
dummy clocks to satisfy drivers requiring clocks..
Clocks whose rates need to be known are supplied by fixed-rate
dummy-clocks that provide the correct rate. This is uncritical insofar
that the only bootloader currently in
Uarts on all recent Rockchip SoCs are Synopsis DesignWare 8250 types.
Only their addresses vary very much.
This patch adds the necessary definitions to use any of the uart ports
for early debug purposes.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
arch/arm/Kconfig.debug| 34
This adds a generic devicetree board file and a dtsi for boards
based on the RK3066a SoCs from Rockchip.
Apart from the generic parts (gic, clocks, pinctrl) the only components
currently supported are the timers, uarts and mmc ports (all DesignWare-
based).
Signed-off-by: Heiko Stuebner
This adds a basic clock setup for rk3066a SoCs. Only the gates are
set up currently, as the mux and dividers should use the upcoming
generic devicetree bindings.
Clocks whose rates need to be known are supplied by fixed-rate
dummy-clocks that provide the correct rate. This is uncritical insofar
Sixth version of basic Rockchip A9 support.
This time again using the regular gate clocks as the driver got accepted into
the clock tree.
Changes since v5:
- reintroduce the use of the gate clocks
Changes since v4:
- remove ifdef around l2x0 init
- only use dummy clocks
Changes since v3:
-
Uarts on all recent Rockchip SoCs are Synopsis DesignWare 8250 types.
Only their addresses vary very much.
This patch adds the necessary definitions to use any of the uart ports
for early debug purposes.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
arch/arm/Kconfig.debug| 34
This adds a generic devicetree board file and a dtsi for boards
based on the RK3066a SoCs from Rockchip.
Apart from the generic parts (gic, clocks, pinctrl) the only components
currently supported are the timers, uarts and mmc ports (all DesignWare-
based).
Signed-off-by: Heiko Stuebner
Am Dienstag, 18. Juni 2013, 10:05:30 schrieb Linus Walleij:
On Mon, Jun 17, 2013 at 8:50 PM, Laurent Pinchart
laurent.pinchart+rene...@ideasonboard.com wrote:
Hello,
Here's the seventh (and hopefully final) version of the SuperH and SH
Mobile pin controllers (PFC) DT support patch
at these too and make sure these cover
what you were doing.
[It seems like Heiko Stübner was not aware of patches in the clock
tree, so did pretty much equivalent patch.]
Correct ... I was going after what was in linux-next and the tip.git [which I
also only saw recently at all] does not seem
Am Dienstag, 18. Juni 2013, 17:38:35 schrieb Heiko Stübner:
Hi Pavel,
Am Dienstag, 18. Juni 2013, 17:02:44 schrieb Pavel Machek:
Hi!
The following 2 patches will eliminate the need for the patch in John
Stultz's tree. If there is to be merge of the 2 trees, then the
patch
Am Montag, 17. Juni 2013, 04:58:23 schrieb Mike Turquette:
Device Tree binding for the basic clock multiplexer, plus the setup
function to register the clock. Based on the existing fixed-clock
binding.
Includes minor beautification of clk-provider.h where some whitespace is
added and
Am Sonntag, 16. Juni 2013, 12:26:38 schrieb Linus Walleij:
On Fri, Jun 14, 2013 at 5:42 PM, Heiko Stübner he...@sntech.de wrote:
The BIAS_DISABLE and BIAS_HIGH_IMPEDANCE generic pinconfig options were
missing information about their argument - which should be ignored.
Also the BIAS_PULL_
Am Sonntag, 16. Juni 2013, 12:35:43 schrieb Linus Walleij:
On Fri, Jun 14, 2013 at 5:44 PM, Heiko Stübner he...@sntech.de wrote:
Change the rockchip pinctrl driver to handle the arguments of 0 or 1 to
the pull pinconfig options correctly, so that the pull gets disabled when
either
Change the rockchip pinctrl driver to handle the arguments to the pull
pinconfig options correctly. So only accept non-0 values for the
pull options as the rockchip pin-controller can only turn pulls on and
off (this via BIAS_DISABLE).
Signed-off-by: Heiko Stuebner he...@sntech.de
---
changes
Am Samstag, 15. Juni 2013, 21:56:05 schrieb Linus Walleij:
On Fri, Jun 14, 2013 at 12:39 AM, Laurent Pinchart
laurent.pinch...@ideasonboard.com wrote:
mmcif_pins: mmcif {
mux {
renesas,groups = mmc0_data8_0,
Some issues with the recently submitted generic pinconfig parsing from dt
came up, so fix these in this follow-up series.
Hopefully I did catch all of them.
Tested on my rk3066 device.
Heiko Stuebner (5):
pinctrl: update the documentation for some pinconfig params
pinctrl: clarify some dt
The bias-pull-* options use values 0 to indicate that the pull should
be activated and optionally also indicate the strength of the pull.
Therefore use an default value of 1 for these options.
Split the low-power-mode option into low-power-enable and -disable.
Update the documentation to
This adds a shortcut when no valid pinconf properties are found
in the parsed dt node, to set the values immediately and return.
Suggested-by: Laurent Pinchart laurent.pinch...@ideasonboard.com
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/pinctrl/pinconf-generic.c |7 +++
1
Allocating the temorary array in pinconf_generic_parse_dt_config on stack
might cause problems later on, when the number of options grows over time.
Therefore also allocate this array dynamically to be on the safe side.
Suggested-by: Laurent Pinchart laurent.pinch...@ideasonboard.com
Change the rockchip pinctrl driver to handle the arguments of 0 or 1 to
the pull pinconfig options correctly, so that the pull gets disabled when
either the bias_disable options is set or the pull option has the argument 0.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
Fourth version of basic Rockchip A9 support.
Changes since v3:
- split out standalone dw_mmc patches (submitted to linux-mmc)
- Remove divider and mux clocks and use fixed rate clocks instead until
divider and mux clocks have got their generic dt bindings
- Make the gate clock use
This adds basic support for gate-clocks on Rockchip SoCs.
There are 16 gates in each register and use the HIWORD_MASK
mechanism for changing gate settings.
The gate registers form a continuos block which makes the dt node
structure a matter of taste, as either all 160 gates can be put into
one
This adds a basic clock setup for rk3066a SoCs. Only the gates are
set up currently, as the mux and dividers should use the upcoming
generic devicetree bindings.
Clocks whose rates need to be known are supplied by fixed-rate
dummy-clocks that provide the correct rate. This is uncritical insofar
Uarts on all recent Rockchip SoCs are Synopsis DesignWare 8250 types.
Only their addresses vary very much.
This patch adds the necessary definitions to use any of the uart ports
for early debug purposes.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
arch/arm/Kconfig.debug| 34
This adds a generic devicetree board file and a dtsi for boards
based on the RK3066a SoCs from Rockchip.
Apart from the generic parts (gic, clocks, pinctrl) the only components
currently supported are the timers, uarts and mmc ports (all DesignWare-
based).
Signed-off-by: Heiko Stuebner
Am Dienstag, 4. Juni 2013, 11:36:09 schrieb Heiko Stübner:
This is split off of my Rockchip support series from yesterday. It's now
a patch more than before, as the third patch enables the timer to be used
thru clocksource_of_init and moves picoxcell and socfpga to it.
changes since v1
Am Dienstag, 11. Juni 2013, 22:06:10 schrieb Mike Turquette:
Quoting Heiko Stübner (2013-06-11 04:31:31)
This adds basic support for clocks on Rockchip rk3066 SoCs.
The clock handling thru small dt nodes is heavily inspired by the
sunxi clk code.
The plls are currently read-only
Am Donnerstag, 13. Juni 2013, 01:02:34 schrieb Olof Johansson:
On Thu, Jun 13, 2013 at 12:45:41AM +0200, Heiko Stübner wrote:
Part of me simply wants to wait for this - but rockchip stuff might be to
late for 3.11 anyway, as we're near rc6.
For a new platform like this, it's useful to get
SoCs like the Rockchip Cortex-A9 ones contain divider some clocks
that use the regular mechanisms for storage but allow only even
dividers and 1 to be used.
Therefore add a flag that lets _is_valid_div limit the valid dividers
to these values. _get_maxdiv is also adapted to return even values
for
Third version of basic Rockchip A9 support.
The biggest change is probably the missing pinctrl driver which already found
its way into the pinctrl tree from Linus Walleij as part of the pinconfig
generalisation and should find its way into the mainline kernel from there.
But startup of
In a subsquent patch probe will need to do some handling of data from
the dt match table. So to prevent the need for forward declarations,
move probe and remove below the match table.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/mmc/host/dw_mmc-pltfm.c | 28
dw_mci_pltfm_remove gets exported and used by dw_mmc-exynos, so should
not be static.
Signed-off-by: Heiko Stuebner he...@sntech.de
Acked-by: Jaehoon Chung jh80.ch...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
---
drivers/mmc/host/dw_mmc-pltfm.c |2 +-
1 files changed, 1
Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc
controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to
always be set.
There also seem to be no other modifications (additional register etc)
present, so to keep the footprint low, add this small variant to the
This adds basic support for clocks on Rockchip rk3066 SoCs.
The clock handling thru small dt nodes is heavily inspired by the
sunxi clk code.
The plls are currently read-only, as their setting needs more
investigation. This also results in slow cpu speeds, as the apll starts
at a default of
Uarts on all recent Rockchip SoCs are Synopsis DesignWare 8250 types.
Only their addresses vary very much.
This patch adds the necessary definitions to use any of the uart ports
for early debug purposes.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
arch/arm/Kconfig.debug| 34
Am Dienstag, 11. Juni 2013, 13:51:56 schrieb Andy Shevchenko:
On Tue, Jun 11, 2013 at 2:29 PM, Heiko Stübner he...@sntech.de wrote:
SoCs like the Rockchip Cortex-A9 ones contain divider some clocks
that use the regular mechanisms for storage but allow only even
dividers and 1 to be used
Am Dienstag, 11. Juni 2013, 20:57:50 schrieb Mike Turquette:
Quoting Heiko Stübner (2013-06-11 04:29:32)
SoCs like the Rockchip Cortex-A9 ones contain divider some clocks
that use the regular mechanisms for storage but allow only even
dividers and 1 to be used.
Therefore add a flag
Am Freitag, 7. Juni 2013, 13:46:32 schrieb Linus Walleij:
On Thu, Jun 6, 2013 at 9:08 PM, Heiko Stübner he...@sntech.de wrote:
There exist platforms, namely at least all Rockchip Cortex-A9 based ones,
that don't use the paradigm of reading-changing-writing the register
contents, but instead
Am Freitag, 7. Juni 2013, 14:53:51 schrieb Linus Walleij:
On Thu, Jun 6, 2013 at 9:11 PM, Heiko Stübner he...@sntech.de wrote:
+ for (i = 0, j = 0; i size; i += 4, j++) {
+ unsigned long pinconf;
+
+ num = be32_to_cpu(*list++);
+ bank
Am Samstag, 8. Juni 2013, 01:13:48 schrieb Heiko Stübner:
Am Freitag, 7. Juni 2013, 14:53:51 schrieb Linus Walleij:
On Thu, Jun 6, 2013 at 9:11 PM, Heiko Stübner he...@sntech.de wrote:
+ for (i = 0, j = 0; i size; i += 4, j++) {
+ unsigned long pinconf
Second version of basic Rockchip A9 support.
Changes since v1:
- addressed Linus Walleij's comments to the pinctrl driver, including the
move to generic pinconfig (hopefully I did catch all)
- renamed the clocks to use the SoC name of the initial user
as suggested by Olof Johansson
- fixed
There exist platforms, namely at least all Rockchip Cortex-A9 based ones,
that don't use the paradigm of reading-changing-writing the register contents,
but instead only write the changes to the register with a mask that indicates
the changed bits.
This patch adds flags and code to support the
SoCs like the Rockchip Cortex-A9 ones contain divider some clocks
that use the regular mechanisms for storage but allow only even
dividers and 1 to be used.
Therefore add a flag that lets _is_valid_div limit the valid dividers
to these values. _get_maxdiv is also adapted to return even values
for
This driver adds support the Cortex-A9 based SoCs from Rockchip,
so at least the RK2928, RK3066 (a and b) and RK3188.
Earlier Rockchip SoCs seem to use similar mechanics for gpio
handling so should be supportable with relative small changes.
Pull handling on the rk3188 is currently a stub, due to
This adds basic support for clocks on Rockchip rk3066 SoCs.
The clock handling thru small dt nodes is heavily inspired by the
sunxi clk code.
The plls are currently read-only, as their setting needs more
investigation. This also results in slow cpu speeds, as the apll starts
at a default of
Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc
controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to
always be set.
There also seem to be no other modifications (additional register etc)
present, so to keep the footprint low, add this small variant to the
Uarts on all recent Rockchip SoCs are Synopsis DesignWare 8250 types.
Only their addresses vary very much.
This patch adds the necessary definitions to use any of the uart ports
for early debug purposes.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
arch/arm/Kconfig.debug| 34
This adds a generic devicetree board file and a dtsi for boards
based on the RK3066a SoCs from Rockchip.
Apart from the generic parts (gic, clocks, pinctrl) the only components
currently supported are the timers, uarts and mmc ports (all DesignWare-
based).
Signed-off-by: Heiko Stuebner
Am Mittwoch, 5. Juni 2013, 16:00:43 schrieb Seungwon Jeon:
On 06/03/13 7:59 AM, Heiko Stübner wrote:
Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc
controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to
always be set.
There also seem to be no other
Am Mittwoch, 5. Juni 2013, 19:18:49 schrieb Stephen Warren:
On 06/05/2013 01:01 AM, Linus Walleij wrote:
On Tue, Jun 4, 2013 at 2:05 PM, Heiko Stübner he...@sntech.de wrote:
...
The only problem is the pull stuff mentioned above that is either pull
up or down without the driver having
Am Dienstag, 4. Juni 2013, 21:22:43 schrieb Mike Turquette:
Quoting Matt Sealey (2013-06-04 10:39:53)
On Tue, Jun 4, 2013 at 12:11 PM, Stephen Boyd sb...@codeaurora.org
wrote:
On 06/03/13 10:53, Mike Turquette wrote:
+Required properties:
+- compatible : shall be divider-clock.
Am Dienstag, 4. Juni 2013, 06:36:20 schrieb Baruch Siach:
Hi Heiko,
On Mon, Jun 03, 2013 at 09:59:55PM +0200, Heiko Stübner wrote:
dw_apb_timer_init used to search the devicetree for matching timer
devices, making calls to it from board files necessary.
Change the dw_apb_timer_init
Am Dienstag, 4. Juni 2013, 08:34:44 schrieb Linus Walleij:
On Mon, Jun 3, 2013 at 12:56 AM, Heiko Stübner he...@sntech.de wrote:
Currently the dw_apb_timer always expects a separate special timer to be
availbable for the sched_clock. Some devices using dw_apb_timers do not
have the sptimer
Am Dienstag, 4. Juni 2013, 06:06:39 schrieb Jaehoon Chung:
On 06/03/2013 07:59 AM, Heiko Stübner wrote:
Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc
controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to
always be set.
There also seem
This is split off of my Rockchip support series from yesterday. It's now
a patch more than before, as the third patch enables the timer to be used
thru clocksource_of_init and moves picoxcell and socfpga to it.
changes since v1:
- hopefully improve the patch description of patch 1
after a
Currently the dw_apb_timer always expects a separate special timer to be
availbable for the sched_clock. Some devices using dw_apb_timers do not
have this sptimer but can use the clocksource as sched_clock instead.
Therefore enable the driver to distiguish between devices with and without
sptimer
dw_apb_timer_of is the driver part facing devicetree platforms and
calls into dw_apb_timer with the data gathered from the dt.
Currently the two platforms using the dw_apb_timer_of select both
the options for the core timer and the dt addon.
As dw_apb_timer_of always depends on dw_apb_timer let
Add the possibility to get the clock-frequency from a timer clock instead
of specifying it as dt property. Additionally also add the possibility
to also define a controlling periphal clock for the timer block.
The clock-frequency property is kept to act as fallback if no clocks
are specified.
dw_apb_timer_init used to search the devicetree for matching timer
devices, making calls to it from board files necessary.
Change the dw_apb_timer_init to work with CLOCKSOURCE_OF_DECLARE.
With this change the function gets called once for each timer node
and tracks these number of calls to
Am Dienstag, 4. Juni 2013, 11:37:02 schrieb Heiko Stübner:
Currently the dw_apb_timer always expects a separate special timer to be
availbable for the sched_clock. Some devices using dw_apb_timers do not
have this sptimer but can use the clocksource as sched_clock instead.
Therefore enable
Hi,
I'll just skip over the right, will fix that issues and just address the
unclear ones.
Am Dienstag, 4. Juni 2013, 09:08:09 schrieb Linus Walleij:
On Mon, Jun 3, 2013 at 12:59 AM, Heiko Stübner he...@sntech.de wrote:
This driver adds support the Cortex-A9 based SoCs from Rockchip,
so
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