From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP is common
across all the ST parts for settop box platforms.
ASC is embedded in ST COMMS IP block. It supports Rx Tx
On 04/07/13 00:04, David Miller wrote:
You are going to have to fix up the following build warnings and resubmit:
CC [M] drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.o
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c: In function
‘stmmac_mdio_reset’:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds phy reset callback support for stmmac driver via device
trees. It adds three new properties to gmac device tree bindings to
define the reset signal via gpio.
With this patch users can conveniently pass reset gpio number
From: Srinivas Kandagatla srinivas.kandaga...@st.com
Hi Peppe/Dave,
Thankyou for the comments on v1 patches.
This patch series adds support to new gmac versions 3.6.10 and 3.710, these
versions of IP are integrated into ST STiH415/STiH416 SOCs.
This patchset also adds phy reset capablity
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds dt support to dwmac version 3.610 and 3.710 these
versions are integrated in STiH415 and STiH416 ARM A9 SOCs.
To support these IP version, some of the device tree properties are
extended.
Signed-off-by: Srinivas Kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@st.com
In some DT use-cases platform data might be already allocated and passed
via AUXDATA. These are the cases where machine level code populates few
callbacks in the platform data.
This patch adds check and reuses platform_data if its valid
Thanks Peppe for the comments,
On 01/07/13 18:20, Giuseppe CAVALLARO wrote:
On 7/1/2013 1:43 PM, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
+
+plat-bus_id = of_alias_get_id(np, ethernet);
+if (plat-bus_id 0)
+plat-bus_id = 0
From: Srinivas Kandagatla srinivas.kandaga...@st.com
In some DT use-cases platform data might be already allocated and passed
via AUXDATA. These are the cases where machine level code populates few
callbacks in the platform data.
This patch adds check and reuses platform_data if its valid
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds dt support to dwmac version 3.610 and 3.710 these
versions are integrated in STiH415 and STiH416 ARM A9 SOCs.
To support these IP version, some of the device tree properties are
extended.
Signed-off-by: Srinivas Kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@st.com
Hi Peppe,
Thankyou for the comments on RFC patches.
This patch series adds support to new gmac versions 3.6.10 and 3.710, these
versions of IP are integrated into ST STiH415/STiH416 SOCs.
This patchset also adds phy reset capablity to stmmac
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds phy reset callback support for stmmac driver via device
trees. It adds three new properties to gmac device tree bindings to
define the reset signal via gpio.
With this patch users can conveniently pass reset gpio number
From: Srinivas Kandagatla srinivas.kandaga...@st.com
Hi Peppe,
This patch series adds support to new gmac versions 3.6.10 and 3.710, these
versions of IP are integrated into ST STiH415/STiH416 SOCs.
This patchset also adds phy reset capablity to stmmac-mdio driver via DT.
Thanks,
srini
From: Srinivas Kandagatla srinivas.kandaga...@st.com
In some DT use-cases platform data might be already allocated and passed
via AUXDATA. These are the cases where machine level code populates few
callbacks in the platform data.
This patch adds check and reuses platform_data if its valid
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds dt support to dwmac version 3.610 and 3.710 these
versions are integrated in STiH415 and STiH416 ARM A9 SOCs.
To support these IP version, some of the device tree properties are
extended.
Signed-off-by: Srinivas Kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds phy reset callback support for stmmac driver via device
trees. It adds three new properties to gmac device tree bindings to
define the reset signal via gpio.
With this patch users can conveniently pass reset gpio number
, Failed pinctrl registration\n);
- return PTR_ERR(info-pctl);
+ return -EINVAL;
}
for (i = 0; i info-nbanks; i++)
Thankyou for the patch, It looks OK.
Acked-by: Srinivas Kandagatla srinivas.kandaga...@st.com
Can you resend it with cc to Mark Brown broo
Thanks for your comments,
On 25/06/13 22:14, Sören Brinkmann wrote:
+Example:
+
+ timer@2c000600 {
+ compatible = arm,cortex-a9-global-timer;
+ reg = 0x2c000600 0x20;
+ interrupts = 1 13 0xf01;
+ };
Isn't a 'clocks' entry missing here?
Yep, I will add it
Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Rob Herring robherri...@gmail.com
CC: Linus Walleij linus.wall...@linaro.org
CC: Will Deacon will.dea
On 26/06/13 14:24, Daniel Lezcano wrote:
If its not too late can this patch be considered for 3.11 via clocksource
tree?
This patch has no build dependencies.
I took it in my tree but it is too late for a 3.11, sorry.
Thanks Daniel.
Thanks
-- Daniel
Thankyou for the comments.
On 24/06/13 23:08, Stephen Boyd wrote:
On 06/24/13 08:53, Srinivas KANDAGATLA wrote:
+#include linux/clkdev.h
Why do you need this include?
+#include asm/mach/irq.h
And this one?
Removed them.
+static u64 gt_counter_read(void)
+{
+u64 counter
Thankyou for the comments,
On 24/06/13 23:00, Stephen Boyd wrote:
On 06/24/13 14:08, Srinivas KANDAGATLA wrote:
On 24/06/13 21:06, Stephen Boyd wrote:
On 06/24/13 08:53, Srinivas KANDAGATLA wrote:
I think the problem is your clockevent has no rating. Please give it a
rating (300?) so
Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
Reviewed-by: Thomas Gleixner t...@linutronix.de
CC: Arnd Bergmann a...@arndb.de
CC: Rob Herring robherri...@gmail.com
CC: Linus Walleij
On 24/06/13 15:12, Mark Brown wrote:
On Mon, Jun 24, 2013 at 01:57:56PM +0200, Linus Walleij wrote:
This seems fairly complete, but I cannot have such a basic dependency onto
the regmap tree this late in the merge window, i.e. I'm not ready to pull
all of regmap into the pinctrl tree. I'd
On 25/06/13 00:38, Greg Kroah-Hartman wrote:
On Mon, Jun 24, 2013 at 08:21:43AM +0100, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP
On 25/06/13 11:58, Linus Walleij wrote:
On Mon, Jun 24, 2013 at 4:12 PM, Mark Brown broo...@kernel.org wrote:
On Mon, Jun 24, 2013 at 01:57:56PM +0200, Linus Walleij wrote:
This seems fairly complete, but I cannot have such a basic dependency onto
the regmap tree this late in the merge
Thanks for the comments.
On 25/06/13 14:17, Thomas Gleixner wrote:
On Tue, 25 Jun 2013, Srinivas KANDAGATLA wrote:
If its not too late can this patch be considered for 3.11 via clocksource
tree?
Sure. No worry, though I noticed a little detail when reading through it
again. See below
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP is common
across all the ST parts for settop box platforms.
ASC is embedded in ST COMMS IP block. It supports Rx Tx
Thankyou for the comments.
On 21/06/13 16:56, Thomas Gleixner wrote:
On Fri, 21 Jun 2013, Srinivas KANDAGATLA wrote:
+static void gt_clockevent_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *clk)
+{
+unsigned long ctrl;
+
+ctrl
On 24/06/13 12:57, Linus Walleij wrote:
On Fri, Jun 21, 2013 at 3:41 PM, Srinivas KANDAGATLA
srinivas.kandaga...@st.com wrote:
Hi Linus W,
If its not too late can this patch be considered for 3.11 via pinctrl tree?
There is a build dependecy with regmap_field apis pulled by Mark Brown
Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Rob Herring robherri...@gmail.com
CC: Linus Walleij linus.wall...@linaro.org
CC: Will Deacon will.dea
On 24/06/13 21:06, Stephen Boyd wrote:
On 06/24/13 08:53, Srinivas KANDAGATLA wrote:
+
+static void gt_clockevents_stop(struct clock_event_device *clk)
+{
+gt_clockevent_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
+disable_percpu_irq(clk-irq);
+}
+
+static int __cpuinit
On 24/06/13 21:01, Thomas Gleixner wrote:
On Mon, 24 Jun 2013, Srinivas KANDAGATLA wrote:
From: Stuart Menefy stuart.men...@st.com
This is a simple driver for the global timer module found in the Cortex
A9-MP cores from revision r1p0 onwards. This should be able to perform
the functions
On 20/06/13 19:55, Arnd Bergmann wrote:
On Thursday 20 June 2013, Srinivas KANDAGATLA wrote:
--- a/arch/arm/mach-sti/board-dt.c
+++ b/arch/arm/mach-sti/board-dt.c
@@ -11,6 +11,7 @@
#include linux/clocksource.h
#include linux/irq.h
#include asm/hardware/cache-l2x0.h
+#include asm
On 20/06/13 20:02, Arnd Bergmann wrote:
On Thursday 20 June 2013, Srinivas KANDAGATLA wrote:
+static u64 gt_counter_read(void)
+{
+ u64 counter;
+ u32 lower;
+ u32 upper, old_upper;
+
+ upper = __raw_readl(gt_base + GT_COUNTER1);
+ do
Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Rob Herring robherri...@gmail.com
CC: Linus Walleij linus.wall...@linaro.org
CC: Will Deacon will.dea
=67252287871113deba96adf7e4df1752f3f08688
Thanks,
srini
On 20/06/13 15:05, Srinivas KANDAGATLA wrote:
This patch add pinctrl support to ST SoCs.
About hardware:
ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
pin configurations.
Each multi-function pin is controlled, driven and routed through
industry standard baud rates.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Greg Kroah-Hartman gre...@linuxfoundation.org
From my point of view the series
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP is common
across all the ST parts for settop box platforms.
ASC is embedded in ST COMMS IP block. It supports Rx Tx
Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Rob Herring robherri...@gmail.com
CC: Linus Walleij linus.wall...@linaro.org
CC: Will Deacon will.dea
The STiH415 is the next generation of HD, AVC set-top box processors for
satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9
1.0 GHz, dual-core CPU.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy
rates.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Greg Kroah-Hartman gre...@linuxfoundation.org
---
.../devicetree/bindings/tty/serial/st-asc.txt | 18
the signal.
About driver:
This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
pinconf, pinmux, gpio subsystems. All the pinctrl related config
information can only come from device trees.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore
The STiH416 is advanced HD AVC processor with 3D graphics acceleration
and 1.2-GHz ARM Cortex-A9 SMP CPU.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Linus
of new SOC addition to
multi_v7_defconfig.
I wanted this to be in a seperate patch, as these options are not
related any of the new SOC support.
Already some discussion at:https://patchwork.kernel.org/patch/2696481
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
arch/arm/configs
This patch adds stih415 and stih416 support to multi_v7_defconfig.
CONFIG_ARM_ERRATA_754322 is removed as it is selected by the sti
mach level kconfig.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
arch/arm/configs/multi_v7_defconfig |4 +++-
1 files changed, 3
a/arch/arm/boot/dts/stih415-b2020.dts
b/arch/arm/boot/dts/stih415-b2020.dts
new file mode 100644
index 000..442b019
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2020.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (RD) Limited.
+ * Author: Srinivas Kandagatla srinivas.kandaga
B2000 board is reference board for STIH415/416 SOCs, it has
2 x UART, 4x USB, 2 x Ethernet, 1 x SATA, 1 x PCIe, and 1GB RAM.
This patch add initial support to b2000 with STiH415/416 with UART2 as
console and a heard beat LED.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC
This patch adds low level debug uart support to sti based SOCs.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
---
arch/arm/Kconfig.debug | 38 +++
arch/arm/include/debug/sti.S | 61
Thankyou very much for the comments.
On 16/06/13 13:17, Linus Walleij wrote:
On Mon, Jun 10, 2013 at 11:22 AM, Srinivas KANDAGATLA
srinivas.kandaga...@st.com wrote:
About driver:
This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
pinconf, pinmux, gpio subsystems. All
On 10/06/13 14:52, Arnd Bergmann wrote:
On Monday 10 June 2013 10:27:05 Srinivas KANDAGATLA wrote:
+ soc {
+ pin-controller-sbc {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = st,stih416-pinctrl, simple
On 10/06/13 17:38, Srinivas Kandagatla wrote:
+++ b/arch/arm/boot/dts/sti-pincfg.h
@@ -0,0 +1,94 @@
+#ifndef _STI_PINCFG_H_
+#define _STI_PINCFG_H_
+
+/* Alternate functions */
+#define ALT1 1
+#define ALT2 2
+#define ALT3 3
+#define ALT4 4
+#define ALT5
On 10/06/13 14:15, Mark Rutland wrote:
CONFIG_EXPERIMENTAL's gone as of 3d374d09f1: final removal of
CONFIG_EXPERIMENTAL, so that's fine to go. CONFIG_GPIO_PL061 and
CONFIG_MMC_WMT get selected elsewhere, so that's fine.
Am planning to send a patch to clean this up, so that any new platform
On 13/06/13 12:56, Russell King - ARM Linux wrote:
On Tue, Jun 11, 2013 at 07:50:31AM +0100, Srinivas KANDAGATLA wrote:
You are right, It does not make sense to use BIT() macro for field which
has more than 1 bit. I think using mix of both BIT() and the old style
will make code look bit
On 11/06/13 21:13, Linus Walleij wrote:
On Tue, Jun 11, 2013 at 4:05 PM, Srinivas KANDAGATLA
srinivas.kandaga...@st.com wrote:
Doing this is not adding any value to the driver, because
1. Currently the driver only support DT boot paths, in my previous RFC
patches, Arnd suggested to get rid
On 11/06/13 00:19, Russell King - ARM Linux wrote:
On Mon, Jun 10, 2013 at 12:46:59PM +0100, Srinivas KANDAGATLA wrote:
+ aux_ctrl = (0x1 L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
+ (0x1 L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
+ (0x1
On 10/06/13 15:02, Arnd Bergmann wrote:
There are multiple ways of doing that, e.g. you could export a function
from syscon.c that you call to register the device node and then import
the regmap from syscon into your high-level driver again.
Hi Arnd/Linus,
Thankyou for your comments,
I did
On 10/06/13 14:41, Srinivas Kandagatla wrote:
On 10/06/13 14:13, Linus Walleij wrote:
On Mon, Jun 10, 2013 at 11:21 AM, Srinivas KANDAGATLA
Isn't it better to pass a struct device_node *np around and have that as
NULL in the non-DT boot path?
I will try it and see how it will look.
I did try
rates.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Greg Kroah-Hartman gre...@linuxfoundation.org
---
.../devicetree/bindings/tty/serial/st-asc.txt | 18
From: Srinivas Kandagatla srinivas.kandaga...@st.com
Here is new patch-set incorporating all the review comments.
This patch-set adds basic support for STMicroelectronics STi SOCs
which includes STiH415 and STiH416 with B2000 and B2020 board support.
STiH415 and STiH416 are dual-core ARM
pinctrl.
This patch adds support to ST System Configuration registers, which can
be configured by the drivers.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stuart Menefy stuart.men...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Linus Walleij linus.wall...@linaro.org
CC
Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Rob Herring robherri...@gmail.com
CC: Linus Walleij linus.wall...@linaro.org
CC: Will Deacon will.dea
the signal.
About driver:
This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
pinconf, pinmux, gpio subsystems. All the pinctrl related config
information can only come from device trees.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore
are based on regmaps,
like some clocks or pinctrls which can work on the regmap_fields
directly without having to worry about bit positions.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Mark Brown broo...@kernel.org
CC: Arnd Bergmann a...@arndb.de
CC: Alexander Shiyan shc_w
a/arch/arm/boot/dts/stih415-b2020.dts
b/arch/arm/boot/dts/stih415-b2020.dts
new file mode 100644
index 000..442b019
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2020.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (RD) Limited.
+ * Author: Srinivas Kandagatla srinivas.kandaga
This patch adds low level debug uart support to sti based SOCs.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
---
arch/arm/Kconfig.debug | 38 +++
arch/arm/include/debug/sti.S | 61
This patch adds stih415 and stih416 support to multi_v7_defconfig.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
---
arch/arm/configs/multi_v7_defconfig | 32 +++-
1 files changed, 15 insertions(+), 17 deletions
B2000 board is reference board for STIH415/416 SOCs, it has
2 x UART, 4x USB, 2 x Ethernet, 1 x SATA, 1 x PCIe, and 1GB RAM.
This patch add initial support to b2000 with STiH415/416 with UART2 as
console and a heard beat LED.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC
The STiH416 is advanced HD AVC processor with 3D graphics acceleration
and 1.2-GHz ARM Cortex-A9 SMP CPU.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Linus
Thanks for testing...
On 10/06/13 11:40, Mark Rutland wrote:
On Mon, Jun 10, 2013 at 10:27:57AM +0100, Srinivas KANDAGATLA wrote:
This patch adds stih415 and stih416 support to multi_v7_defconfig.
This seems to drop a few options also:
CONFIG_ARM_ARCH_TIMER
Same as last comment 2
Thankyou for your comment and suggestion,
I will fix the POSIX compliant issue.
On 10/06/13 10:35, Russell King - ARM Linux wrote:
On Mon, Jun 10, 2013 at 10:21:00AM +0100, Srinivas KANDAGATLA wrote:
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically
On 10/06/13 14:13, Linus Walleij wrote:
On Mon, Jun 10, 2013 at 11:21 AM, Srinivas KANDAGATLA
srinivas.kandaga...@st.com wrote:
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Rob Herring
On 10/06/13 14:16, Linus Walleij wrote:
On Mon, Jun 10, 2013 at 11:22 AM, Srinivas KANDAGATLA
srinivas.kandaga...@st.com wrote:
This mfd driver provides higher level inialization routines for various
IPs like Ethernet, USB, PCIE, SATA and so on. Also it provides way to
get to syscfg
Thanks for the comments.
On 10/06/13 15:02, Arnd Bergmann wrote:
On Monday 10 June 2013 14:52:38 Srinivas KANDAGATLA wrote:
On 10/06/13 14:16, Linus Walleij wrote:
On Mon, Jun 10, 2013 at 11:22 AM, Srinivas KANDAGATLA
srinivas.kandaga...@st.com wrote:
This mfd driver provides higher level
Thankyou for your comments.
On 10/06/13 14:52, Arnd Bergmann wrote:
On Monday 10 June 2013 10:27:05 Srinivas KANDAGATLA wrote:
+soc {
+pin-controller-sbc {
+#address-cells = 1;
+#size-cells = 1;
+compatible
On 10/06/13 13:43, Linus Walleij wrote:
On Mon, Jun 10, 2013 at 11:26 AM, Srinivas KANDAGATLA
srinivas.kandaga...@st.com wrote:
The STiH415 is the next generation of HD, AVC set-top box processors for
satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9
1.0 GHz, dual
On 23/05/13 22:44, Arnd Bergmann wrote:
Thankyou Arnd for extending this discussion.
On Monday 20 May 2013, Srinivas KANDAGATLA wrote:
On 17/05/13 15:36, Arnd Bergmann wrote:
On the other hand using device trees to describe the HW
configuration(sysconfs) made more sense and got rid of SOC
Hi Arnd,
Thankyou for the comments.
On 17/05/13 15:36, Arnd Bergmann wrote:
On Thursday 09 May 2013, Srinivas KANDAGATLA wrote:
On 08/05/13 20:48, Arnd Bergmann wrote:
I agree, my initial approach was having a dedicated driver specific to
ST syscon, however syscon seems to do things very much
Thankyou for the comments.
On 13/05/13 20:05, Linus Walleij wrote:
On Wed, May 8, 2013 at 4:11 PM, Srinivas KANDAGATLA
srinivas.kandaga...@st.com wrote:
Thomas Gleixner and John Stultz should always be included on timer code
review.
This is one reason I really like to move
On 14/05/13 10:23, Linus Walleij wrote:
On Tue, May 14, 2013 at 10:46 AM, Srinivas KANDAGATLA
srinivas.kandaga...@st.com wrote:
On 13/05/13 20:05, Linus Walleij wrote:
Why are you enabling the timer in unused and shutdown mode?
This doesn't make sense.
It is because we are using
-of-tree kernel.
http://git.stlinux.com/?p=stm/linux-stm.git;a=blob;f=drivers/stm/sysconf.c
Any suggestions?
thanks,
srini
On 09/05/13 10:51, Mark Brown wrote:
On Wed, May 08, 2013 at 06:42:04PM +0100, Srinivas KANDAGATLA wrote:
Fix your mailer to word wrap within paragraphs.
Ultimately
Hi Arnd,
Thankyou for extending the discussion.
On 08/05/13 20:48, Arnd Bergmann wrote:
On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
the pinctrl driver calls syconf_claim(np, st,alt-control) to get a
field and then do a read/write on the field.
Just in pinctrl driver we use around 50
On 09/05/13 10:51, Mark Brown wrote:
On Wed, May 08, 2013 at 06:42:04PM +0100, Srinivas KANDAGATLA wrote:
Fix your mailer to word wrap within paragraphs.
Sorry about that.
Ultimately the syscon_write use the regmap_update_bits, however we
really want is the flexibility in using/referring
On 09/05/13 14:26, Mark Brown wrote:
On Thu, May 09, 2013 at 12:58:01PM +0100, Srinivas KANDAGATLA wrote:
Currently, we have two bits of information which come from device trees.
1 The syscon bank/group definition itself.
2 syscon register offsets and bits information to the drivers
On 08/05/13 15:38, Arnd Bergmann wrote:
On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
From: Stuart Menefy stuart.men...@st.com
This is a simple driver for the global timer module found in the Cortex
A9-MP cores from revision r1p0 onwards. This should be able to perform
the functions
On 09/05/13 15:40, Mark Brown wrote:
So what exactly is the driver doing then? If the register maps look
nothing like each other then what's the common functionality the driver
is providing?
What I meant here is that, sysconf registers are reassigned per SOC, so
the sysconf register
On 09/05/13 15:51, Arnd Bergmann wrote:
It won't.
Looking at the code in clocksource_of_init it just goes through the
of_device_id table, which is not used in case of non-DT.
All new platforms are DT-only, and none of the old platforms use this
driver, so it does not matter.
It makes
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch-set adds basic support for STMicroelectronics STiH41x SOCs
which includes STiH415 and STiH416 with B2000 and B2020 board support.
STiH415 and STiH416 are dual-core ARM Cortex-A9 CPU, designed for use in
Set-top-boxes.
The SOC
Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
Documentation/devicetree/bindings/arm/gt.txt | 21 ++
arch/arm/Kconfig |6 +
arch/arm/include/asm
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP is common
across all the ST parts for settop box platforms.
ASC is embedded in ST COMMS IP block. It supports Rx Tx
From: Srinivas Kandagatla srinivas.kandaga...@st.com
The STiH416 is advanced HD AVC processor with 3D graphics acceleration
and 1.2-GHz ARM Cortex-A9 SMP CPU.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men
From: Srinivas Kandagatla srinivas.kandaga...@st.com
B2000 board is reference board for STIH415/416 SOCs, it has
2 x UART, 4x USB, 2 x Ethernet, 1 x SATA, 1 x PCIe, and 1GB RAM.
This patch add initial support to b2000 with STiH415/416 with UART2 as
console and a heard beat LED.
Signed-off
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch add pinctrl support to ST SoCs.
About hardware:
ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
pin configurations.
Each multi-function pin is controlled, driven and routed through the PIO
multiplexing
From: Srinivas Kandagatla srinivas.kandaga...@st.com
B2020 ADI board is reference board for STIH415/416 SOCs, it has 2 x
UART, 4x USB, 1 x Ethernet, 1 x SATA, 1 x PCIe, and 2GB RAM with
standard set-top box IPs.
This patch adds initial support to B2020 with STiH415/416 with SBC_UART1
as console
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch introduces syscon_claim, syscon_read, syscon_write,
syscon_release APIs to help drivers to use syscon registers in much more
flexible way.
With this patch, a driver can claim few/all bits in the syscon registers
and do read/write
Thankyou for the comments.
On 08/05/13 16:06, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 15:11 Wed 08 May , Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch add pinctrl support to ST SoCs.
About hardware:
ST Set-Top-Box parts have two blocks
Thankyou for the comments.
On 08/05/13 17:18, Arnd Bergmann wrote:
On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
The STiH415 is the next generation of HD, AVC set-top box processors for
satellite, cable, terrestrial and IP-STB
On 08/05/13 17:20, Arnd Bergmann wrote:
On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
diff --git a/arch/arm/mach-stih41x/board-dt.c
b/arch/arm/mach-stih41x/board-dt.c
index 8005f71..1f23aca 100644
--- a/arch/arm/mach-stih41x/board-dt.c
+++ b/arch/arm/mach-stih41x/board-dt.c
@@ -63,6
Thankyou for your comments.
On 08/05/13 15:50, Arnd Bergmann wrote:
On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch introduces syscon_claim, syscon_read, syscon_write,
syscon_release APIs to help drivers to use syscon
Thankyou for the comments.
On 08/05/13 16:01, Mark Brown wrote:
On Wed, May 08, 2013 at 04:50:22PM +0200, Arnd Bergmann wrote:
In many cases a single syconf register contains bits related to multiple
devices, and therefore it need to be shared across multiple drivers at
bit level. The same IP
Thankyou for the comments.
On 08/05/13 15:34, Arnd Bergmann wrote:
On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
+*st-asc(Serial Port)
+
+Required properties:
+- compatible : Should be st,asc.
Are there any hardware revision
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