Does it mean that pci is supposed be always 64 bit wide?
And there is no option to have just 32bit values.
I certainly believe that all PCIe (not PCI) transfers are
nominally multiples of 64bit data.
There are (effectively) 8 byte-lane enables to allow partial word
transfers (I'm not sure
On Wed, Dec 12, 2012 at 10:49 AM, Grant Likely wrote:
On Wed, Dec 12, 2012 at 10:37 AM, Michal Simek
mon...@monstr.eumailto:mon...@monstr.eu wrote:
On 12/10/2012 10:41 PM, Grant Likely wrote:
drivers/pci/pci-of.c would be good. I'd also accept drivers/of/pci.c
which might actually be a
On Wed, Dec 12, 2012 at 01:34:24PM +, Thierry Reding wrote:
On Wed, Dec 12, 2012 at 12:19:12PM +, Andrew Murray wrote:
I've been working on a relatively architecture agnostic PCI host bridge
driver
and also wanted to avoid duplicating more generic DT parsing code for PCI
On 12/10/2012 10:41 PM, Grant Likely wrote:
On Mon, 10 Dec 2012 09:21:51 -0600, Rob Herring robherri...@gmail.com wrote:
On 12/10/2012 09:05 AM, Michal Simek wrote:
On 12/10/2012 03:26 PM, Rob Herring wrote:
On 12/10/2012 06:20 AM, Michal Simek wrote:
Hi Grant and others,
I have a question
On Wed, Dec 12, 2012 at 10:37 AM, Michal Simek mon...@monstr.eu wrote:
On 12/10/2012 10:41 PM, Grant Likely wrote:
drivers/pci/pci-of.c would be good. I'd also accept drivers/of/pci.c
which might actually be a good idea in the short term so that it gets
appropriate supervision while being
On Wed, Dec 12, 2012 at 12:19:12PM +, Andrew Murray wrote:
On Wed, Dec 12, 2012 at 10:49 AM, Grant Likely wrote:
On Wed, Dec 12, 2012 at 10:37 AM, Michal Simek
mon...@monstr.eumailto:mon...@monstr.eu wrote:
On 12/10/2012 10:41 PM, Grant Likely wrote:
drivers/pci/pci-of.c would be
Dear Rob Herring,
On Mon, 10 Dec 2012 17:24:44 -0600, Rob Herring wrote:
Marvell SoCs have up to 20 configurable address windows, which allow
you, at run time, to say I would like the range from physical
address 0x to 0x to correspond to the PCIe device
in port 1, lane 2,
On 12/12/2012 11:49 AM, Grant Likely wrote:
On Wed, Dec 12, 2012 at 10:37 AM, Michal Simek mon...@monstr.eu wrote:
On 12/10/2012 10:41 PM, Grant Likely wrote:
drivers/pci/pci-of.c would be good. I'd also accept drivers/of/pci.c
which might actually be a good idea in the short term so that it
On Wed, Dec 12, 2012 at 4:16 PM, Thomas Petazzoni
thomas.petazz...@free-electrons.com wrote:
Dear Rob Herring,
On Mon, 10 Dec 2012 17:24:44 -0600, Rob Herring wrote:
Marvell SoCs have up to 20 configurable address windows, which allow
you, at run time, to say I would like the range from
On 12/12/2012 10:16 AM, Thomas Petazzoni wrote:
Dear Rob Herring,
On Mon, 10 Dec 2012 17:24:44 -0600, Rob Herring wrote:
Marvell SoCs have up to 20 configurable address windows, which allow
you, at run time, to say I would like the range from physical
address 0x to 0x to
On 12/10/2012 06:20 AM, Michal Simek wrote:
Hi Grant and others,
I have a question regarding number of cells in ranges property
for pci and pcie nodes.
Linux pci/pcie powerpc DTSes contain 7 cells (xpedite5370.dts,
sequoia.dts, etc)
but also 6 cells format too (mpc832x_mds.dts)
Here
On 12/10/2012 03:26 PM, Rob Herring wrote:
On 12/10/2012 06:20 AM, Michal Simek wrote:
Hi Grant and others,
I have a question regarding number of cells in ranges property
for pci and pcie nodes.
Linux pci/pcie powerpc DTSes contain 7 cells (xpedite5370.dts,
sequoia.dts, etc)
but also 6 cells
On 12/10/2012 09:05 AM, Michal Simek wrote:
On 12/10/2012 03:26 PM, Rob Herring wrote:
On 12/10/2012 06:20 AM, Michal Simek wrote:
Hi Grant and others,
I have a question regarding number of cells in ranges property
for pci and pcie nodes.
Linux pci/pcie powerpc DTSes contain 7 cells
On 12/10/2012 04:21 PM, Rob Herring wrote:
On 12/10/2012 09:05 AM, Michal Simek wrote:
On 12/10/2012 03:26 PM, Rob Herring wrote:
On 12/10/2012 06:20 AM, Michal Simek wrote:
Hi Grant and others,
I have a question regarding number of cells in ranges property
for pci and pcie nodes.
Linux
On 12/10/2012 09:37 AM, Michal Simek wrote:
On 12/10/2012 04:21 PM, Rob Herring wrote:
On 12/10/2012 09:05 AM, Michal Simek wrote:
On 12/10/2012 03:26 PM, Rob Herring wrote:
On 12/10/2012 06:20 AM, Michal Simek wrote:
Hi Grant and others,
I have a question regarding number of cells in
On 12/10/2012 04:52 PM, David Laight wrote:
Does it mean that pci is supposed be always 64 bit wide?
And there is no option to have just 32bit values.
I certainly believe that all PCIe (not PCI) transfers are
nominally multiples of 64bit data.
And PCI? That powerpc/pci-common code was
On 12/10/2012 05:02 PM, Rob Herring wrote:
On 12/10/2012 09:37 AM, Michal Simek wrote:
On 12/10/2012 04:21 PM, Rob Herring wrote:
On 12/10/2012 09:05 AM, Michal Simek wrote:
On 12/10/2012 03:26 PM, Rob Herring wrote:
On 12/10/2012 06:20 AM, Michal Simek wrote:
Hi Grant and others,
I have a
Dear Michal Simek,
On Mon, 10 Dec 2012 17:05:13 +0100, Michal Simek wrote:
CC: Thomas: I think it will be interesting to see this discussion
because you are using size-cell/address-cells equal 1.
http://www.spinics.net/lists/arm-kernel/msg211839.html
Thanks for Cc'ing me.
The thing is that
On Mon, 10 Dec 2012 16:37:26 +0100, Michal Simek mon...@monstr.eu wrote:
On 12/10/2012 04:21 PM, Rob Herring wrote:
On 12/10/2012 09:05 AM, Michal Simek wrote:
On 12/10/2012 03:26 PM, Rob Herring wrote:
On 12/10/2012 06:20 AM, Michal Simek wrote:
Hi Grant and others,
I have a question
On Mon, 10 Dec 2012 09:21:51 -0600, Rob Herring robherri...@gmail.com wrote:
On 12/10/2012 09:05 AM, Michal Simek wrote:
On 12/10/2012 03:26 PM, Rob Herring wrote:
On 12/10/2012 06:20 AM, Michal Simek wrote:
Hi Grant and others,
I have a question regarding number of cells in ranges
On Mon, 2012-12-10 at 21:43 +, Grant Likely wrote:
Sorry for my pci ignorance (have never got hw for mb/zynq)
I just want to get better overview how we should we our drivers to
be compatible.
Does it mean that pci is supposed be always 64 bit wide?
And there is no option to have
On 12/10/2012 12:38 PM, Benjamin Herrenschmidt wrote:
On Mon, 2012-12-10 at 21:43 +, Grant Likely wrote:
Sorry for my pci ignorance (have never got hw for mb/zynq)
I just want to get better overview how we should we our drivers to
be compatible.
Does it mean that pci is supposed be
On 12/10/2012 11:15 AM, Thomas Petazzoni wrote:
Dear Michal Simek,
On Mon, 10 Dec 2012 17:05:13 +0100, Michal Simek wrote:
CC: Thomas: I think it will be interesting to see this discussion
because you are using size-cell/address-cells equal 1.
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