Hi,
I am very very new to USRP.. I have followed the instructions on
SuseInstall and then BuildGuide. I do not know what to do next?
I am running Suse 10.2 and have got the USRP mother board with RX2400
daughter boards.
Hope to hear from anyone with ideas on what to do next! It would be
gr
2007/8/8, [EMAIL PROTECTED] <[EMAIL PROTECTED]>:
> I've been using Ubuntu with much better results. You'll spend less time
> fixing the OS and more time on doing GNU radio stuff.
>
>
>
> On Tue, 7 Aug 2007, Marcus Leech wrote:
>
> > I'm considering upgrading my receiver 'puter (a Dual-core Pentium
G'day,
I've just committed gnuradio-3.0.4 into the pkgsrc tree which should become
availabe shortly.
It may be of interest to some of you to know that GNU Radio was successfully
built on hardware platforms such as Alpha, I386, SPARC64, SPARC and X86_64.
The NetBSD Packages Collection (pkgsrc)
I've been using Ubuntu with much better results. You'll spend less time
fixing the OS and more time on doing GNU radio stuff.
On Tue, 7 Aug 2007, Marcus Leech wrote:
> I'm considering upgrading my receiver 'puter (a Dual-core Pentium
> system) from FC6 to Fedora7.
>
> Anything I need to know
Johnathan Corgan wrote:
Brian Padalino wrote:
I haven't taken a look at the daughterboards, but do they all use
different amplifiers and different numbers of stages?
They are mostly different. All the RFX boards are similar, but the RFX
uses a different front end from the TVRX, DBSRX and t
Brian Padalino wrote:
> I haven't taken a look at the daughterboards, but do they all use
> different amplifiers and different numbers of stages?
They are mostly different. All the RFX boards are similar, but the RFX
uses a different front end from the TVRX, DBSRX and the new boards still
in de
On 8/7/07, Johnathan Corgan <[EMAIL PROTECTED]> wrote:
> It's a "digital RSSI" value, meaning it's based on the output of the ADC
> and not the true RF power at the antenna. Furthermore, it's really a
> single pole low pass averaging filter on the absolute value of the ADC
> value, with no way to
Brian Padalino wrote:
> Is this really the RSSI - or should the RSSI actually be a function of
> the amount of gain or attenuation in the RF stages? I am sure it gets
> pretty difficult calculating an estimate for the amount of power at
> the antenna.
It's a "digital RSSI" value, meaning it's ba
On 8/7/07, Zhuocheng Yang <[EMAIL PROTECTED]> wrote:
> Hi guys:
>
> I noticed that in the adc_interface, there are registers called rssi_0,
> rssi_1, rssi_2, and rssi_3. All of which are 32 bits. However, according to
> the header format:
> http://gnuradio.org/trac/browser/gnuradio/trunk/usrp/doc
Reid-
> I've written a small Verilog module for the FPGA on the USRP to do phase
> recovery. I'd like to test it in isolation before I try it out on the board,
> but I'm having major problems feeding Quartus two 16 bit sine and cosine
> signals with a random phase offset. The idea is that q_out
On 8/7/07, Reid N Kleckner <[EMAIL PROTECTED]> wrote:
> Hello,
>
> I've written a small Verilog module for the FPGA on the USRP to do phase
> recovery. I'd like to test it in isolation before I try it out on the board,
> but I'm having major problems feeding Quartus two 16 bit sine and cosine
> si
Hi guys:
I noticed that in the adc_interface, there are registers called rssi_0, rssi_1,
rssi_2, and rssi_3. All of which are 32 bits. However, according to the header
format:
http://gnuradio.org/trac/browser/gnuradio/trunk/usrp/doc/inband-signaling-usb
The rssi should be 6 bits. Do I just use t
Ismail Mohamed wrote:
> My question is, with the LFTX/RX boards, is the communication truly
> baseband such that frequency synchronisation can be totally ignored?
Not quite.
With the LFTX/RX boards, DC does indeed remain DC at the other end.
However, the crystals in each USRP still govern the sa
Brian Padalino wrote:
On 8/3/07, Zhuocheng Yang <[EMAIL PROTECTED]> wrote:
You haven't really modeled what the board is doing properly, so your
code is probably doing exactly what it should in the circumstances
you're giving to it. You should get a dump of the raw packets
George's server i
Reid N Kleckner wrote:
> Or do people just burn their Verilog code to the board to test it?
For pre-synthesis, RTL simulation and testing, I use Icarus Verilog
under Linux.
--
Johnathan Corgan
Corgan Enterprises LLC
http://corganenterprises.com
___
Hello,
I've written a small Verilog module for the FPGA on the USRP to do phase
recovery. I'd like to test it in isolation before I try it out on the board,
but I'm having major problems feeding Quartus two 16 bit sine and cosine
signals with a random phase offset. The idea is that q_out after t
I'm considering upgrading my receiver 'puter (a Dual-core Pentium
system) from FC6 to Fedora7.
Anything I need to know for Gnu Radio?
I've already noticed that Firefox 2.0.0.5 is *very* flakey on Fedora
7--crashes without provocation every few
minutes. [If anyone here happens to know the fix f
Thanks, Chris and Eric, for the help so far. I was finally able to pass the
usrp1_source_c_sptr smart pointer into my c++ code. I have one more step that
I still can't seem to figure out:
I want to call functions on the smart pointer, but the functions are not
getting linked into my c++ code.
Hi!
Probably, I have found a bug in the way you create buffers for outgoing
block connections.
First, this is what I have:
A hier-block2, with a gr_block inside, encapsulating some computations.
Inner connections: self.connect(self, ofdm_preamble, self)
where ofdm_preamble is a gr_block of mine.
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