Hi Jeffrey,
thanks for the advice. The standard power of USRP2 should be enough
for me, if I really get it :)
In the specifications for XCVR2450 it says 100mW or 20 dBm.
The jamming is already working, but a bit more power would be fine ;)
Yesterday I moved the micaz node around my USRP2 to find
Hi,
I am writing a block to concatenated data from two input streams of
different length and i am using following I/O signatures
ACS_combine_vff::ACS_combine_vff(int len)
: gr_sync_block(ACS_combine_vff,
gr_make_io_signature(1,2, sizeof(float)*len),
Hi Jeffrey,
thanks for the advice. The standard power of USRP2 should be enough
for me, if I really get it :)
In the specifications for XCVR2450 it says 100mW or 20 dBm.
The jamming is already working, but a bit more power would be fine ;)
Yesterday I moved the micaz node around my USRP2
Oops,
I read that it was usrp1.
Do I understand correctly that this is similar to gr-gpio? I thought
VRT allowed separate streams, why are the bits still in the LSB of I
and Q? Does this also work with UHD?
How about dual DDC? Any news about dual DDC for usrp2? How easy would
it be to add this
Juha,
Do I understand correctly that this is similar to gr-gpio? I thought
VRT allowed separate streams, why are the bits still in the LSB of I
and Q? Does this also work with UHD?
I'm using pre-UHD/VRT code at the moment - my understanding is the metadata
VRT adds applies to a group of
On 06/23/2010 05:37 AM, Tim Pearce wrote:
Juha,
Do I understand correctly that this is similar to gr-gpio? I thought
VRT allowed separate streams, why are the bits still in the LSB of I
and Q? Does this also work with UHD?
I'm using pre-UHD/VRT code at the moment - my understanding is
Dear list,
Here is a paper I submitted to EURASIP Journal on Advances in Signal
Processing, special issue on Cooperative MIMO Multicell Networks in
case somebody is interested. The paper is entitled Experimental
Investigation of TDD Reciprocity Based Zero-Forcing Transmit Precoding.
Hi,
I am currently working on a project were i have to detect a frequency, lock
into it and then decode the signal. I tried to use gnuradio but i faced a
lot of problems such as the speed of scanning the signal or the accuracy of
detecting the signal. I am now trying to implement that into a
hi all
I have access to a USRP2 board. I recently loaded the new firmware and fpga
images onto it, which have UHD support i.e. To be precise, the firmware
image was the one released on 21st june and the fpga image was the one
released on the 15th of june, found on the Ettus website.
I have been
hi all
I have access to a USRP2 board. I recently loaded the new firmware and
fpga images onto it, which have UHD support i.e. To be precise, the
firmware image was the one released on 21st june and the fpga image
was the one released on the 15th of june, found on the Ettus website.
I have
find_usrps wont do you any good, its for raw ethernet gr-libusrp2
You probably have a network setup issue:
http://www.ettus.com/uhd_docs/manual/html/usrp2.html#setup-networking
I recommend disabling firewall, setting your static IP. If you still
have issues use wireshark and/or a serial
Dear all,
Is it possible to change the sampling rate of D/A converter to 64MHz? I saw the
sampling rate of D/A converter is defined in usrp_basic.cc, which is
fpga_master_clock_freq() * 2. Is it possible to make the master clock frequency
not multiply by 2? Can it be changed in python when the
Setting up the Static IP worked.. thanks for all the help..
Abhi
On Wed, Jun 23, 2010 at 1:36 PM, Josh Blum j...@joshknows.com wrote:
find_usrps wont do you any good, its for raw ethernet gr-libusrp2
You probably have a network setup issue:
On Wed, Jun 23, 2010 at 11:27 AM, Yan Nie yn...@uwo.ca wrote:
Is it possible to change the sampling rate of D/A converter to 64MHz? I saw
the sampling rate of D/A converter is defined in usrp_basic.cc, which is
fpga_master_clock_freq() * 2. Is it possible to make the master clock
frequency not
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