Hi all,
It's a little bit off-topic but if someone will change the gr-osmosdr,
it would be great to have other stream tags that we are used to see at
the output UHD source. For example if the source prints on the output
that there is some problem with transmission it would be great to add a
Hello all,
I have been trying to understand the mechanics of stream tags and USRP. To
this end, I am reading through the tags_demo.cc example found in
gr-uhd/examples/c++.
The example provides two options for burst control: using SOB/EOB tags, and
using tagged stream blocks. For clarity, let us
When you say differential, what does it mean? To me something differential
is something that has only 2 levels (like 0 and 180 degrees). If it's the
case, how can you tell it ?
When you say "channel" what do you mean ?
I'm sorry if it seems difficult for me because it is right now. I'm trying
to
I've explained that multiple times already. You're doing a differential
phase shift keying, and as long as there's no channel between your
pseudo-FSK transmitter and your quadrature demod, the quadrature demod's
output will actually be the same phase difference. Please, let the
1Sample per symbol
I'm aware of all this. This is why I asked because I don't understand why
with 1 sps I can recover my entire message with no trouble but when it
comes to a higher sps I can't. This afternoon I tried something with a MM
clock recovery (with 6 sps). In simulation it gave me somewhat of a good
any way you do this, if you're using quadrature demod, you must also not
reduce the sample number until *after* you demodulated your FSK signal.
Again, for something to actually have a frequency, you'd need it to have
a derivable phase. Derivation needs more than one sample.
Best regards,
Your flowgraph intrinsically has one symbol per sample in the data generation
portion. You need a resampler just ahead of the throttle to interpolate in
order to increase the number of samples per symbol.
@(^.^)@ Ed
Sent from my iPhone
> On Jul 21, 2016, at 3:15 PM, Olivier Goyette
In the spirit of voiding the warranty, physically invert the LVDS clock input
and output traces at the ADS62P48 with haywire and x-acto knife; the FPGA
may then not know the difference. Use it as sub-device A:AB at the full 200
Msps, then interleave the complex parts into a real stream once in
Hi Olivier,
as discussed, an FSK with 1 S/symbol is not really an FSK; so I can't
really confirm that it does what you want (it does do some DPSK, in
fact). 6 S/symbol mean that one symbol, ie. the duration for which the
output frequency is held constant, is six samples, nothing more, nothing
Hi Olivier,
as discussed, an FSK with 1 S/symbol is not really much of an FSK; so I
can't really confirm that it does what you want (it does do some DPSK,
in fact).
When you decimate something by a factor of six, the resampler has to
choose a filter that kills the upper 5/6 of the spectrum,
Lou,
Many high-speed data converters actually interleave samples from multiple
lower speed ADCs. They delay clock, rather than the signal, which is much
easier. Even then, unless the delay is perfect, you get really bad spurs.
Mismatches in delay on the order of 100 fs can be a big problem.
So
Hi all !
I've been working on this flowgraph for a while now and I've been able to
pinpoint what is not working, but I don't understand how to resolve this
so, that's why i'm asking for your guidance.
Take a look at the flowgraph i've joined. The thing that doesn't seem to be
working on this
Goodmorning,
I would like to Know some methods to Close flowgraph automatically when
it has finished. Some example, stop when USRP has no more samples to
transmits, or a file source has read until EOF.
The Run of completion option works when (for instance) you have a file
source connected to
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