Dear List,
Can we capture two or more frequency simultaneously by using USRP ?
regards
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r so. We'll be making it
public in the next couple of weeks and would appreciate input.
--
Nikhil
.:..thinkRF
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y are not being able to do. I have
tried using a single antenna with auto tr mode enabled. I have also tried to
use two separate antennas at different frequencies however none of these
work. I would appreciate it if someone could guide me regarding th
support for USB2.0 and Ethernet
interfaces.
We'll have a few beta units available this fall, so if you're interested
in details, feel free to get in touch.
Nikhil
The OMAP has some interesting interfaces and I wonder if some of them
could be adapted for a more general I/O use. I a
re than adequate. And
between successive "probes" you have enough time to transfer the captured
sequence over the USB at a slower rate than the max. sampling rate of 64
MSamples per second in the Rx. But this assumes you can store about 2kB of
data on the FPGA.
Nikhil
> So for i
On Fri, Jul 25, 2008 at 9:57 PM, Johnathan Corgan <
[EMAIL PROTECTED]> wrote:
> On Fri, Jul 25, 2008 at 6:12 PM, Nikhil <[EMAIL PROTECTED]> wrote:
>
> > I'm curious -- in a channel sounder application what benefit, if any is
> > there to performing the cros
On Thu, Jul 24, 2008 at 4:37 PM, Johnathan Corgan <
[EMAIL PROTECTED]> wrote:
> On Thu, Jul 24, 2008 at 12:30 PM, Nikhil <[EMAIL PROTECTED]> wrote:
>
> > Are you trying to measure the impulse response of the channel? If so,
> then
> > one technique would be to t
low-pass
received signal with the known m-sequence to give the (complex) impulse
response of the channel. Any 'peaks' that exceed your definition of a
threshold noise level would be your channel coefficients in the time domain.
Nikhil
>
>
> I am planning on using the conjug
On 5/24/07, Lin HUANG <[EMAIL PROTECTED]> wrote:
Hi everybody,
Hello,
2. The TX side: For the power supply circuit, U111 ADP3336 has input 6V
and output 5V and U110 has 5V input and 3.3V output. For the
AD8349, VCC=5V, and ADF4360 has VCC=3.3V. They all seem normal. But when
we run the
te_fpga_reg(FR_DEBUG_EN, bmFR_DEBUG_EN_RX_B | bmFR_DEBUG_EN_TX_B)
and then in usrp_std.v
master_control master_control
(
//.debug_0(rx_a_a),.debug_1(ddc0_in_i),
.debug_0(rx_debugbus),.debug_1(ddc0_in_i),
.debug_2(rx_a_a),.debug_3(rx_b_a), .... );
schematics, respectively. Can someone
please explain?
Thanks very much in advance!
-Nikhil
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Thanks for posting this -- very useful indeed.
Minor fix on the Tx chain: I think the ADF4360 PLL feeds the LO port(s) of the Quad. Mod.
cheers.
nikhil
On 8/29/06, Lee Patton <[EMAIL PROTECTED]> wrote:
I've taken a shot at coming up with block diagrams for the USRP andRF
On 7/26/06, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
I'd vote for Gigabit Ethernet as an interface. It offers the following:
Since you mention Gigabit Ethernet, I have to ask... are there any latency issues with it?
Nikhil
With this chip we're expecting to achieve a throughput of about 90 MByte/second. You can try the 9056 if this doesn't meet your bandwidth requirements.
Cheers.
Nikhil
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