to
use to create a custom solution to serve your needs.
Al
On May 29, 2012 6:17 PM, Page Jack jack.page...@gmail.com wrote:
I don't want to using a ethernet wire to connect N series to an ARM
board.
anyone have tried
build N series with ARM or DSP in one board which means the ethernet line
09:18 PM, Page Jack wrote:
Hi Philip,
How does the conclusion be made that ARM can not swallow the current
max data transfer rate? I need to build a project that need to process
60MB/s data, so any way to achieve my goal. Use a more powerful CPU or
use dsp on the omap?
60 MB/s is far
:
On 05/24/2012 09:46 PM, Page Jack wrote:
Thanks Ben,
does e100 use EMIF to transfer sample data between FPGA and ARM? If so
the
data rate should be able to improved.
Anyone have tried to improve the data rate?
EMIF is basically identical to GPMC. The interface uses DMA to move data
in 2K
Hi all,
what is the aux dac and aux adc in ad9862 used for in usrp?
Regards
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Thanks Marcus.
On Fri, Nov 25, 2011 at 4:59 PM, Marcus M gnu.f...@gmail.com wrote:
Frequency is irrelevant. If you want to send two signals on the same
medium then you are basically adding them together.
On Thu, Nov 24, 2011 at 11:47 PM, Page Jack jack.page...@gmail.comwrote:
Hi list,
I
Hi list,
I want to send two signal which at different frequency. Can I simply add
these two signals' sample to generate a new signal
which mix the two signal?
Regards!
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Why no one have the answer or have the same question?
On Fri, Aug 12, 2011 at 9:52 AM, Page Jack jack.page...@gmail.com wrote:
Hi all,
I have some problems when compile the fpga source.
I open uhd-git\fpga\usrp1\toplevel\usrp_std\usrp_std.qpf with quartus II
then compile meet a lot of errors
Marcus,
thanks for your reply, the different build generate exactly the same
binaries which just
not the same with the binary in uhd git repo.
On Thu, Sep 15, 2011 at 9:37 AM, Marcus D. Leech mle...@ripnet.com wrote:
**
On 14/09/11 09:31 PM, Page Jack wrote:
Why no one have the answer
Hi Tom,
the xlating filter work fine, the phase shift is cause by another factor.
Thanks for your
reply.
On Sun, Aug 14, 2011 at 4:17 AM, Tom Rondeau trondeau1...@gmail.com wrote:
On Fri, Aug 12, 2011 at 3:50 AM, Page Jack jack.page...@gmail.com wrote:
I use xlating filter to down convert
I use xlating filter to down convert signal. after I down convert signal it
I decode it.
however the data decoded is still the signal in 0 frequency before down
convert.
I check the xlating filter code it will change the signal phase to avoid
aliasing, yeah
it avoid aliasing but it is not the data
Hi all,
I have some problems when compile the fpga source.
I open uhd-git\fpga\usrp1\toplevel\usrp_std\usrp_std.qpf with quartus II
then compile meet a lot of errors which is the path error like that:
Error (10054): Verilog HDL File I/O error at rx_buffer.v(25): can't open
Verilog Design File
Hi Colby,
I don't understand why compute RSSI need an IIR filter? as I know the rssi
can be compute
like that: (sample[0]*sample[0]+...sample[i]*sample[i]) / (i+1)
Regards!
On Thu, Aug 4, 2011 at 2:44 PM, Colby Boyer colby.bo...@gmail.com wrote:
On Wed, Aug 3, 2011 at 6:30 PM, Page Jack
Hi Colby,
I know cheaper in hardware, but now I don't understand how using IIR filter
can compute the RSSI?
On Fri, Aug 5, 2011 at 9:18 AM, Colby Boyer colby.bo...@gmail.com wrote:
Cheaper in hardware. You only need one adder.
On Thu, Aug 4, 2011 at 6:13 PM, Page Jack jack.page...@gmail.com
the code below is in sdr_lib/rssi.v I don't understand especially this line:
rssi_int = #1 rssi_int + abs_adc - rssi_int[25:10];
wire [11:0] abs_adc = adc[11] ? ~adc : adc;
reg [25:0] rssi_int;
always @(posedge clock)
if(reset | ~enable)
rssi_int = #1 26'd0;
else
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