on the host has died or closed.
>
> Matt
>
>
>
> On 06/14/2011 11:52 AM, Tiago Rogério Mück wrote:
> > Hi,
> >
> > Have anyone taken a look at this ?
> >
> > We are still struggling to find a solution to this problem. Any tip
> > would help a
Hi,
Have anyone taken a look at this ?
We are still struggling to find a solution to this problem. Any tip would
help a lot.
Thanks,
Tiago
Em 27 de maio de 2011 16:51, Tiago Rogério Mück escreveu:
> Hi,
>
> We have been working with an (old) USRP1 and doing some modifications in
&
Hello,
Have you tried the new Xilinx's FIFOs ?
All constraints were met after regenerating the FIFOs using Fifo Generator
6.1.
I used ise12 branch and compiled the raw ethernet code.
2010/6/1 Matt Ettus
>
>
> The USRP2 FPGA image can now be built with ISE 12.x. ISE 11.x probably
> also works
Well, it seems the aeMB guys are working on a new version of the the core.
Maybe the new core will perform better.
Em 14 de maio de 2010 18:17, Brian Padalino escreveu:
> 2010/5/14 Tiago Rogério Mück :
> > Hello,
> >
> > It seems that everyone is having troubles with ISE
Hello,
It seems that everyone is having troubles with ISE 11.x, but has anyone
tried the new ISE 12 ?
We have successfully synthesized the USRP2 fpga code with ISE 12.1, but we
got a timing error and the bitstream didn't seem to work: find_usrps didn't
find anything and the leds didn't flash.
We
Good to hear that.
Thank you.
2009/9/16 Eric Blossom :
> On Wed, Sep 16, 2009 at 04:40:33PM -0300, Tiago Rogério Mück wrote:
>> Hello,
>>
>> We are working on a custom FPGA build that is going to need more then
>> the 32 registers available for user's builds. I l
Hello,
We are working on a custom FPGA build that is going to need more then
the 32 registers available for user's builds. I looked at
fpga_regs_standard.v/fpga_regs_common.v and
seems that the registers 96-127 are not being used. Is there a problem
in using these registers ? Or in extending the r
Thanks for the answer.
I'm going to start working on it soon and then I'll come back here with the
results (or with the problems :)
2009/6/15 Eric Blossom
> On Wed, Jun 10, 2009 at 04:59:24PM -0300, Tiago Rogério Mück wrote:
> > Hi all,
> >
> > I'm working
Anyone ?
2009/6/10 Tiago Rogério Mück
> Hi all,
>
> I'm working on some experiments using the USRP2, and the 32 Kb available
> for the firmware won't be enough for my experiments. I'll need to modify the
> FPGA code so I can use the 1 MB SRAM for both instruction
Hi all,
I'm working on some experiments using the USRP2, and the 32 Kb available for
the firmware won't be enough for my experiments. I'll need to modify the
FPGA code so I can use the 1 MB SRAM for both instructions and data for the
aeMB, but I'm a bit lost on how I can do this modifications.
I
I'm having some problems using the USRP2 timer. I tested the timer_test.c
and it's not setting a new time to interrupt after the firsts interrupt is
triggered. It doesn't work if the new time is set inside de timer ISR. If I
try to set the new time inside the main function using something like this
p/u2_rev3/u2_rev3.ucf" Line
326: 'CLOCK_DEDICATED_ROUTE' is an invalid constraint name.
Commenting that constraint solves the problem and the project builds fine. I
uploaded the bitstream to the usrp2 and it seems to be OK.
Are these the errors related to the bugs in ISE 9.1 that yo
gt; 2009/5/8 Tiago Rogério Mück :
> > Hi all,
> >
> > I'm trying to open the ISE project in gnuradio/usrp2/fpga/top/u2_fpga and
> it
> > seems some files are missing.
> >
> > I'm using ISE 9.1i and it first converts the project to version 9.1 and
>
Hi all,
I'm trying to open the ISE project in gnuradio/usrp2/fpga/top/u2_fpga and it
seems some files are missing.
I'm using ISE 9.1i and it first converts the project to version 9.1 and then
I got the annexed error.
<>___
Discuss-gnuradio mailing list
I've wrote an application that have two flow graphs as follows: usrp2_source
-> fir -> file_sink. The only difference between the two are the usrp2
frequency and decimation rate.
As you can see in the annexed code, I start the first flow graph, five
seconds latter it stops and the second one start
line 97, in __init__
> > >
> > > self.u.set_decim(decim_rate=(decim * 1.5))
> > > File "/usr/local/lib/python2.5/site-packages/gnuradio/usrp2.py", line
> 499,
> > > in set_decim
> > > return _usrp2.usrp2_source_32fc_sptr_set_decim(self, *args, **kwargs)
> >
Updated from the trunk and I'm not getting that msg anymore.
Everything seems to be ok now.
2009/4/3 Eric Blossom
> On Fri, Apr 03, 2009 at 10:45:18AM -0300, Tiago Rogério Mück wrote:
> > I fixed the problem. The top_block on bbn_80211b_tx_port was not being
> >
?
I'm sending the working code.
2009/4/2 Tiago Rogério Mück
> Hi all,
>
> I'm trying to port the tx code to the usrp2 based on Colby's branch and i'm
> having some problems. The program freezes when the 3rd packet is being sent.
>
> The program uses a gr.me
Hi all,
I'm trying to port the tx code to the usrp2 based on Colby's branch and i'm
having some problems. The program freezes when the 3rd packet is being sent.
The program uses a gr.message_source to buffer the packets and convert them
into a data flow to the modulator, and the problem is that,
Hi,
Guys, I want to start doing some experiments with SDR using the USRP and I
have some doubts.
To begin with, I'd like to replicate the experiment described in this paper:
http://www.inf.ufsc.br/~tiagorm/Thomas_Schmid_PAPER.pdf , and would like to
know what hardware you recommend(USRP1 or 2, th
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