Matt,
So it is possible to be implemented in code on the verilog side? If so, do you
have any suggestions on where to start?
Thanks for your help
Regards,
Benjamin Dannan
Quoting Matt Ettus <[EMAIL PROTECTED]>:
> [EMAIL PROTECTED] wrote:
> > Brian,
> >
> > If you refer to the usrp\fpga\sdr_lib\
[EMAIL PROTECTED] wrote:
Brian,
If you refer to the usrp\fpga\sdr_lib\adc_interface.v
this is a comment stating: \\level sensing for AGC
on line 67 of the verilog code file.
I have read on the wiki that AGC can be implemented by moving resistors around,
can you elaborate on this: which resisto
Brian,
Can AGC be implemented in code, on the verilog side using the FPGA?
Thanks
-Benjamin
uoting Brian Padalino <[EMAIL PROTECTED]>:
> On Mon, Dec 1, 2008 at 10:53 PM, <[EMAIL PROTECTED]> wrote:
> >
> > I am trying to achieve a goal of controlling the AGC, please help.
> >
> > Here is what
Brian,
If you refer to the usrp\fpga\sdr_lib\adc_interface.v
this is a comment stating: \\level sensing for AGC
on line 67 of the verilog code file.
I have read on the wiki that AGC can be implemented by moving resistors around,
can you elaborate on this: which resistors, and on what board?
I a
On Mon, Dec 1, 2008 at 10:53 PM, <[EMAIL PROTECTED]> wrote:
>
> I am trying to achieve a goal of controlling the AGC, please help.
>
> Here is what I have so far, for the automatic gain control (AGC):
>
> I have found in the module adc_interface (which is in
> fpga\sdr_lib\adc_interface) a comment
