[Bug 94679] DAL DCE 10 missing CEA interlaced modes

DAL would have also had them. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160323/a95e35b9/attachment-0001.html>

[Bug 86351] HDMI audio garbled output on Radeon R9 280X

https://bugzilla.kernel.org/show_bug.cgi?id=86351 --- Comment #23 from Andy Furniss --- I don't have a 270X anymore which I was using when first commenting in this bug. My current R9285 Tonga also has this issue and I've just tried setting 2048 (runtime) for prealloc and it doesn't help me. I

[Bug 94671] [radeonsi] Blue-ish textures in Shadow of Mordor

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[Bug 86351] HDMI audio garbled output on Radeon R9 280X

https://bugzilla.kernel.org/show_bug.cgi?id=86351 --- Comment #22 from Alex Deucher --- This should be re-assigned to the audio driver then. -- You are receiving this mail because: You are watching the assignee of the bug.

[Bug 94671] [radeonsi] Blue-ish textures in Shadow of Mordor

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[Bug 86351] HDMI audio garbled output on Radeon R9 280X

https://bugzilla.kernel.org/show_bug.cgi?id=86351 --- Comment #21 from Christian Birchinger --- I was under the impression, that i already gave feedback about the "Pre-allocated buffer size" value, but i guess i did not. Anyway, a value of 2048 seems to fix the issue. I've tried normal stereo,

[PATCH] drm: Add support for EDID injection.

Allow the possibility to return an copy of the injected EDID when the connector has been forced and an EDID has been specified over the debugfs interface. Signed-off-by: Marius Vlad --- drivers/gpu/drm/drm_edid.c | 23 --- 1 file changed, 20 insertions(+), 3 deletions(-)

[Bug 80419] XCOM: Enemy Unknown Causes lockup

vel/attachments/20160323/0eb36752/attachment-0001.html>

[RFC 1/5] drm: Add DRM support for tiny LCD displays

Hey On Wed, Mar 16, 2016 at 2:34 PM, Noralf Trønnes wrote: > tinydrm provides a very simplified view of DRM for displays that has > onboard video memory and is connected through a slow bus like SPI/I2C. > > Signed-off-by: Noralf Trønnes > --- > drivers/gpu/drm/Kconfig

[RFC 1/5] drm: Add DRM support for tiny LCD displays

On Wed, Mar 23, 2016 at 06:07:56PM +0100, Noralf Trønnes wrote: > > Den 18.03.2016 18:47, skrev Daniel Vetter: > >On Thu, Mar 17, 2016 at 10:51:55PM +0100, Noralf Trønnes wrote: > >>Den 16.03.2016 16:11, skrev Daniel Vetter: > >>>On Wed, Mar 16, 2016 at 02:34:15PM +0100, Noralf Trønnes wrote:

[RFC 1/5] drm: Add DRM support for tiny LCD displays

Den 18.03.2016 18:47, skrev Daniel Vetter: > On Thu, Mar 17, 2016 at 10:51:55PM +0100, Noralf Trønnes wrote: >> Den 16.03.2016 16:11, skrev Daniel Vetter: >>> On Wed, Mar 16, 2016 at 02:34:15PM +0100, Noralf Trønnes wrote: tinydrm provides a very simplified view of DRM for displays that

[PATCH v3 19/19] ARM: sun5i: chip: Enable the TV Encoder

The CHIP has a composite output available muxed with the microphone in the micro-jack plug. Enable the composite output in its DTS. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-r8-chip.dts | 12 1 file changed, 12 insertions(+) diff --git

[PATCH v3 18/19] ARM: sun5i: r8: Add display blocks to the DTSI

The TCON, tv-encoder and display engine backends and frontends are combined to create our display pipeline. Add them to the R8 DTSI. It's supposed to be perfectly compatible with the A10s and A13, but since we haven't tested it on them yet, it's safer to just enable it on the R8. Eventually, it

[PATCH v3 17/19] drm: sun4i: tv: Add NTSC output standard

Add the settings to support the NTSC standard. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_tv.c | 45 1 file changed, 45 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c index

[PATCH v3 16/19] drm: sun4i: tv: Add PAL output standard

Now that we have support for the composite output, we can start adding new supported standards. Start with PAL, and we will add other eventually. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_tv.c | 42 1 file changed, 42 insertions(+)

[PATCH v3 15/19] drm: sun4i: Add composite output

Some Allwinner SoCs have an IP called the TV encoder that is used to output composite and VGA signals. In such a case, we need to use the second TCON channel. Add support for that TV encoder. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/Makefile | 2 +

[PATCH v3 14/19] drm: sun4i: Add RGB output

One of the A10 display pipeline possible output is an RGB interface to drive LCD panels directly. This is done through the first channel of the TCON that will output our video signals directly. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/Makefile | 1 +

[PATCH v3 13/19] drm: sun4i: Add DT bindings documentation

The display pipeline of the Allwinner A10 is involving several loosely coupled components. Add a documentation for the bindings. Signed-off-by: Maxime Ripard --- .../bindings/display/sunxi/sun4i-drm.txt | 254 + 1 file changed, 254 insertions(+) create mode

[PATCH v3 12/19] drm: Add Allwinner A10 Display Engine support

The Allwinner A10 and subsequent SoCs share the same display pipeline, with variations in the number of controllers (1 or 2), or the presence or not of some output (HDMI, TV, VGA) or not. Add a driver with a limited set of features for now, and we will hopefully support all of them eventually

[PATCH v3 11/19] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS

Add support for the Olimex LCD-OLinuXino-4.3TS panel to the DRM simple panel driver. It is a 480x272 panel connected through a 24-bits RGB interface. Signed-off-by: Maxime Ripard Acked-by: Rob Herring --- .../display/panel/olimex,lcd-olinuxino-43-ts.txt | 7 ++

[PATCH v3 10/19] drm: fb: Add seq_file definition

Otherwise, building with DEBUG_FS enabled will trigger a build warning because we're using a structure that has not been declared. Signed-off-by: Maxime Ripard --- include/drm/drm_fb_cma_helper.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/drm_fb_cma_helper.h

[PATCH v3 09/19] ARM: sun5i: Add TV encoder gate to the DTSI

It turns out that the A13 / R8 also have a tve encoder block, and a gate for it. Add it to the DT. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a13.dtsi | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git

[PATCH v3 08/19] ARM: sun5i: Add DRAM gates

The DRAM gates control whether the image / display devices on the SoC have access to the DRAM clock or not. Enable it. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13.dtsi | 22 +- arch/arm/boot/dts/sun5i-r8.dtsi | 2 +- 2 files changed, 22 insertions(+), 2

[PATCH v3 07/19] ARM: sun5i: a13: Add display and TCON clocks

Enable the display and TCON (channel 0 and channel 1) clocks that are going to be needed to drive the display engine, tcon and TV encoders. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13.dtsi | 38 +-

[PATCH v3 06/19] ARM: sun5i: dt: Add pll3 and pll7 clocks

Enable the pll3 and pll7 clocks in the DT that are used to drive the display-related clocks. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i.dtsi | 43 +++ 1 file changed, 43 insertions(+) diff --git

[PATCH v3 05/19] dt-bindings: clk: sun5i: add DRAM gates compatible

The Allwinner SoCs have a gate controller to gate the access to the DRAM clock to the some devices that need to access the DRAM directly (mostly display / image related IPs). Use a simple gates driver to support the one found in the A13 / R8 SoCs. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu

[PATCH v3 04/19] clk: sunxi: Add TCON channel1 clock

The TCON is a controller generating the timings to output videos signals, acting like both a CRTC and an encoder. It has two channels depending on the output, each channel being driven by its own clock (and own clock controller). Add a driver for the channel 1 clock. Signed-off-by: Maxime

[PATCH v3 03/19] clk: sunxi: Add PLL3 clock

The A10 SoCs and relatives have a PLL controller to drive the PLL3 and PLL7, clocked from a 3MHz oscillator, that drives the display related clocks (GPU, display engine, TCON, etc.) Add a driver for it. Acked-by: Rob Herring Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard ---

[PATCH v3 02/19] clk: sunxi: Add display and TCON0 clocks driver

The A10 SoCs and its relatives has a special clock controller to drive the display engines (both frontend and backend), that have a lot in common with the clock to drive the first TCON channel. Add a driver to support both. Signed-off-by: Maxime Ripard Acked-by: Rob Herring ---

[PATCH v3 01/19] clk: composite: Add unregister function

The composite clock didn't have any unregistration function, which forced us to use clk_unregister directly on it. While it was already not great from an API point of view, it also meant that we were leaking the clk_composite structure allocated in clk_register_composite. Add a

[PATCH v3 00/19] drm: Add Allwinner A10 display engine support

Hi everyone, The Allwinner SoCs (except for the very latest ones) all share the same set of controllers, loosely coupled together to form the display pipeline. Depending on the SoC, the number of instances of the controller will change (2 instances of each in the A10, only one in the A13, for

[Bug 80419] XCOM: Enemy Unknown Causes lockup

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[Bug 94667] Artifacts on applications on discrete

ail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160323/e74cc4cd/attachment.html>

[Bug 94667] Artifacts on applications on discrete

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[Bug 94667] Artifacts on applications on discrete

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Who is going to merge it [Was: Re: [PATCH v14 0/17] Add Analogix Core Display Port Driver]

of the panel tree, but I have no objections at all for this to go in via one of the trees where it is used and can actually be tested. Thierry -- next part -- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160323/2b09a436/attachment.sig>

[PATCH] dma-buf: Update docs for SYNC ioctl

Hi On Wed, Mar 23, 2016 at 12:56 PM, Chris Wilson wrote: > On Wed, Mar 23, 2016 at 12:30:42PM +0100, David Herrmann wrote: >> My question was rather about why we do this? Semantics for EINTR are >> well defined, and with SA_RESTART (default on linux) user-space can >> ignore it. However,

[PATCH] adv7511: Set picture aspect ratio

As of current version the picture aspect ratio and active aspect ratio are not being set when the video mode changes. This patch fixes this problem by setting the picture aspect ratio according to the current video mode and also sets the active aspect ratio to be the same as picture aspect ratio.

[RFC 00/29] De-stage android's sync framework

On 19 January 2016 at 17:12, John Harrison wrote: > On 19/01/2016 15:23, Gustavo Padovan wrote: >> >> Hi Daniel, >> >> 2016-01-19 Daniel Vetter : >> >>> On Fri, Jan 15, 2016 at 12:55:10PM -0200, Gustavo Padovan wrote: From: Gustavo Padovan This patch series de-stage the sync

[RFC 6/6] drm/fence: support fence_collection on atomic commit

From: Gustavo Padovan Let atomic_commit() wait on a collection of fences before proceed with the scanout. Signed-off-by: Gustavo Padovan --- drivers/gpu/drm/drm_atomic.c| 9 + drivers/gpu/drm/drm_atomic_helper.c | 9 +

[RFC 5/6] dma-buf/fence: add fence_collection_wait()

From: Gustavo Padovan Iterate over the array of fences and wait for all of the to finish. Signed-off-by: Gustavo Padovan --- drivers/dma-buf/fence.c | 16 include/linux/fence.h | 1 + 2 files changed, 17 insertions(+) diff --git

[RFC 4/6] dma-buf/fence: add fence_collection_put()

From: Gustavo Padovan Put fence_collection data. For that calls fence_put() on all fences and the user put callback. Signed-off-by: Gustavo Padovan --- drivers/dma-buf/fence.c | 17 + include/linux/fence.h | 2 ++ 2 files changed, 19

[RFC 2/6] dma-buf/fence: add struct fence_collection

From: Gustavo Padovan The struct aggregates fences that we need to wait on before proceed with some specific operation. In DRM, for example, we may wait for a group of fences to signal before we scanout the buffers related to those fences. Signed-off-by: Gustavo

[RFC 1/6] drm/fence: add FENCE_FD property to planes

From: Gustavo Padovan FENCE_FD can now be set by the user during an atomic IOCTL, it will be used by atomic_commit to wait until the sync_file is signalled, i.e., the framebuffer is ready for scanout. Signed-off-by: Gustavo Padovan ---

[RFC 0/6] drm/fences: add in-fences to DRM

From: Gustavo Padovan Hi, This is a first proposal to discuss the addition of in-fences support to DRM. It adds a new struct to fence.c to abstract the use of sync_file in DRM drivers. The new struct fence_collection contains a array with all fences that a

[PATCH] dma-buf: Update docs for SYNC ioctl

On Wed, Mar 23, 2016 at 04:32:59PM +0100, David Herrmann wrote: > Hi > > On Wed, Mar 23, 2016 at 12:56 PM, Chris Wilson > wrote: > > On Wed, Mar 23, 2016 at 12:30:42PM +0100, David Herrmann wrote: > >> My question was rather about why we do this? Semantics for EINTR are > >> well defined, and

[PATCH v3 1/2 RESEND] drm/dp_helper: add workarounds from intel_dp_dpcd_read_wake()

Some sinks need some time during the process of resuming the system from sleep before they're ready to handle transactions. While it would be nice if they responded with NACKs in these scenarios, this isn't always the case as a few sinks will just timeout on all of the transactions they receive.

[PATCH v3 1/2] drm/dp_helper: add workarounds from intel_dp_dpcd_read_wake()

Some sinks need some time during the process of resuming the system from sleep before they're ready to handle transactions. While it would be nice if they responded with NACKs in these scenarios, this isn't always the case as a few sinks will just timeout on all of the transactions they receive.

[PATCH 02/23] ARM: dts: n950: add display support

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[PATCH 02/23] ARM: dts: n950: add display support

On Thu, 17 Mar 2016, Sebastian Reichel wrote: > On Thu, Mar 17, 2016 at 02:14:26PM +0200, Laurent Pinchart wrote: >> [...] >> > + >> > + /* panel is 480x464 with top and bottom 5 lines not visible */ >> >> I assume you mean 480x864 ? > > Yes, nice catch. Basically the screen is 480x864,

[PATCH 6/6] drm/exynos: convert clock_enable crtc callback to pipeline clock

clock_enable callback is used only by FIMD->DP pipeline. Similar but more universal functionality provides pipeline clock. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos_dp_core.c | 8 ++-- drivers/gpu/drm/exynos/exynos_drm_drv.h | 5 -

[PATCH 5/6] drm/exynos/mixer: enable HDMI-PHY before configuring MIXER

According to documentation HDMI-PHY must be on prior to MIXER configuration. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos_mixer.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index

[PATCH 4/6] drm/exynos/decon5433: enable HDMI-PHY before configuring DECON

According to documentation and tests HDMI-PHY must be on prior to MIXER configuration. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c

[PATCH 3/6] drm/exynos/hdmi: expose HDMI-PHY clock as pipeline clock

HDMI-PHY clock should be accessible from other components in the pipeline. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos_hdmi.c | 67 ++-- 1 file changed, 48 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c

[PATCH 2/6] drm/exynos: add support for pipeline clock to the framework

Components belonging to the same pipeline often requires synchronized clocks. Such clocks are sometimes provided by external clock controller, but they can be also provided by pipeline components. In latter case there should be a way to access them from another component belonging to the same

[PATCH 1/6] drm/exynos: add helper to get crtc from pipe

The helper abstracts out conversion from pipeline to crtc. Currently it is used in two places, but there will be more uses in next patches. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos_drm_crtc.c | 10 -- drivers/gpu/drm/exynos/exynos_drm_drv.h | 8 2 files

[PATCH 0/6] drm/exynos: add pipeline clock support

Hi Inki, In case of some pipielines there is need to set clock in one component by driver of another component, for example: 1. Decon and Mixer driver must enable HDMI-PHY clock before configuration. 2. DP driver must enable DP clock provided by FIMD. This set of patches provide more generic

[PATCH 7/7] drm/exynos/decon5433: do not protect window in plane disable

decon_atomic_begin and decon_atomic_flush protects all windows already. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c

[PATCH 6/7] drm/exynos/decon5433: reset decon on start

Resetting IP at starting ensures that DECON will be in known state regardless of changes by bootloader. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c

[PATCH 5/7] drm/exynos/decon5433: fix DECON standalone update

DECON should be updated after un-protecting windows and after changing output parameters, otherwise image is not displayed in case of HDMI path. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-)

[PATCH 4/7] drm/exynos/hdmi: remove registry dump

HDMI registry dump unnecessary spoils console and is not very helpful. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos_hdmi.c | 263 --- 1 file changed, 263 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c

[PATCH 3/7] drm/exynos/hdmi: add core reset code

To ensure HDMI-PHY reprogramming will not affect HDMI the latter should be reset. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos_hdmi.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index

[PATCH 2/7] drm/exynos/hdmi: add PHY power off signal handling

HDMI-PHY power off bit defaults to 0 in older HDMI versions. In case of Exynos5433 it defaults to 1. To make code consistent across all versions this bit is always unset/set in power on/off sequences. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos_hdmi.c | 4 1 file

[PATCH 1/7] drm/exynos/hdmi: fix PHY configuration sequence

Proper PHY configuration should be as follow: 1. set HDMI clock parents to OSCCLK. 2. reconfigure PHY. 3. set HDMI clock parents to PHY. 4. wait for PLL stabilization. The patch fixes it and consolidates the code. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos_hdmi.c | 22

[PATCH 0/7] drm/exynos: HDMI and DECON fixes and enhancements

Hi Inki, This set of patches provides set of different fixes and enhancements for DECON -> HDMI path. It is based on: - my HDMI patches which are not yet merged[1], could you look at them by the way, they were posted about 5 months ago :) - IOMMU patches by Marek (for some mysterious reason

[Bug 94671] [radeonsi] Blue-ish textures in Shadow of Mordor

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[PATCH v2 13/18] mm/compaction: support non-lru movable page migration

On Tue, Mar 22, 2016 at 11:55:45PM +0900, Minchan Kim wrote: > On Tue, Mar 22, 2016 at 02:50:37PM +0900, Joonsoo Kim wrote: > > On Mon, Mar 21, 2016 at 03:31:02PM +0900, Minchan Kim wrote: > > > We have allowed migration for only LRU pages until now and it was > > > enough to make high-order

[Bug 115141] radeon kernel module hangs suspend

https://bugzilla.kernel.org/show_bug.cgi?id=115141 Alex Deucher changed: What|Removed |Added CC||alexdeucher at gmail.com --- Comment #3

[PATCH 52/52] drm/amd/dal: Enable Polaris support in the Kconfig

Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/dal/Kconfig | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/dal/Kconfig b/drivers/gpu/drm/amd/dal/Kconfig index b108756..939d5c6 100644 --- a/drivers/gpu/drm/amd/dal/Kconfig +++

[PATCH 51/52] drm/amdgpu: add dal support for polaris

Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +- drivers/gpu/drm/amd/amdgpu/vi.c| 79 ++ 2 files changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

[PATCH 50/52] drm/amd/dal/dm: add polaris support

Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 20 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c index 1564485..5b3edb8 100644 ---

[PATCH 49/52] drm/amd/dal: add core support for Polaris family (v2)

This adds core dc support for polaris 10 and 11. v2: add missing files Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/dal/dc/Makefile|4 + drivers/gpu/drm/amd/dal/dc/adapter/Makefile|4 + .../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 12 +

[PATCH 48/52] drm/amdgpu: add polaris10/11 smc fw declaration

From: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vi.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c

[PATCH 47/52] drm/amd/powerplay: Disable Spread Spectrum on DPM 0 on baffin as SPLL Shut Down feature is enabled.

From: Rex Zhu Signed-off-by: Rex Zhu Acked-by: Flora Cui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 6 ++ drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 1 + 2 files changed, 7 insertions(+) diff --git

[PATCH 46/52] drm/amd/powerplay: enable set lowest mclk clock on baffin.

From: Rex Zhu Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

[PATCH 45/52] drm/amd/powrplay: fix issue that get wrong enable flag.

From: Rex Zhu Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

[PATCH 44/52] drm/amd/powerplay: fix mclk in high clock for baffin

From: Rex Zhu Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

[PATCH 43/52] drm/amd/powerplay: print gpu loading and uvd/vce power gate enablement for polaris10/11.

From: Rex Zhu Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

[PATCH 41/52] drm/amdgpu: add ELM/BAF pci ids

From: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Alex Deucher Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

[PATCH 40/52] drm/amdgpu: update the core VI support for ELM/BAF

From: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 + drivers/gpu/drm/amd/amdgpu/vi.c| 87 ++ 2 files changed, 89 insertions(+) diff --git

[PATCH 39/52] drm/amdgpu: ungate SMC clockgating first before suspend

From: Flora Cui 46c34bcb6a15dd85329a39a5e72c62108626acdc put all block’s clockgating support in SMC. The sequence in suspend routine should be adjusted accordingly, otherwise it causes asic hang. Signed-off-by: Flora Cui Reviewed-by: Eric Huang ---

[PATCH 38/52] drm/amd/amdgpu: add power gating init for Baffin

From: Eric Huang Reviewed-by: Alex Deucher Signed-off-by: Eric Huang --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 39 +++ 1 file changed, 39 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

[PATCH 37/52] drm/amd/amdgpu: add power gating initialization support for GFX8.0

From: Eric Huang Signed-off-by: Eric Huang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 14 ++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 353 +- 2 files changed, 364 insertions(+), 3 deletions(-) diff --git

[PATCH 36/52] drm/amd/powerplay: add default clockgating handling

From: Flora Cui This is to workaround regression introduced in 46c34bcb6a15dd85329a39a5e72c62108626acdc. It should be reverted with a final fix. Signed-off-by: Flora Cui Reviewed-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 6 -- 1 file changed, 4

[PATCH 35/52] drm/amd/amdgpu: add medium grain powergating support for Baffin

From: Eric Huang Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Eric Huang --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 95 +++ 1 file changed, 95 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

[PATCH 34/52] drm/amd/powerplay: add GFX per cu powergating for Baffin

From: Eric Huang Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Eric Huang --- .../powerplay/hwmgr/ellesmere_clockpowergating.c | 28 ++ .../powerplay/hwmgr/ellesmere_clockpowergating.h | 1 +

[PATCH 33/52] drm/amd/powerplay: add GFX per cu powergating support through SMU/powerplay

From: Eric Huang Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Eric Huang --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 15 ++- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 + 2 files changed, 15 insertions(+), 1

[PATCH 32/52] drm/amd/amdgpu: add query GFX cu info in CGS query system info

Needed for per CU powergating. Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Eric Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 5 + drivers/gpu/drm/amd/include/cgs_common.h | 1 + 2 files changed, 6 insertions(+) diff --git

[PATCH 31/52] drm/amd/powerplay: add GFX/SYS clockgating support for ELM/BAF

From: Eric Huang Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Eric Huang --- .../powerplay/hwmgr/ellesmere_clockpowergating.c | 247 + .../powerplay/hwmgr/ellesmere_clockpowergating.h | 2 +

[PATCH 30/52] drm/amd/powerplay: add all blocks clockgating support through SMU/powerplay

From: Eric Huang Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Eric Huang --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 81 +++ drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 3 + 2 files changed, 84

[PATCH 29/52] drm/amd/powerplay: update baffin & ellesmere smc_sk firmware.

From: yanyang1 sync the code form catalyst CL:#1230866. Signed-off-by: yanyang1 Rviewed-by: Alex Deucher --- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c | 51 ++- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h | 1 +

[PATCH 28/52] drm/amd/powerplay: Add smc_sk firmware to baffin & ellesmere.

From: yanyang1 update relational h files. Signed-off-by: yanyang1 Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h| 1 + drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h| 10 --

[PATCH 27/52] drm/amd/amdgpu: Add smc_sk firmware in baffin & ellesmere.

From: yanyang1 add CGS_UCODE_ID_SMU_SK. Signed-off-by: yanyang1 Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 12 +--- drivers/gpu/drm/amd/include/cgs_common.h | 1 + 2 files changed, 10 insertions(+), 3 deletions(-) diff --git

[PATCH 26/52] drm/amd/powerplay: add UVD DPM and powergating support for elm/baf

From: Eric Huang Signed-off-by: Eric Huang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 3 +- .../powerplay/hwmgr/ellesmere_clockpowergating.c | 153 + .../powerplay/hwmgr/ellesmere_clockpowergating.h |

[PATCH 25/52] drm/amd/powerplay: add thermal control for elm/baf

From: Eric Huang Signed-off-by: Eric Huang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c | 39 +- .../drm/amd/powerplay/hwmgr/ellesmere_thermal.c| 711

[PATCH 24/52] drm/amd/powerplay: enable powerplay for baffin.

From: Rex Zhu Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c index 3cb6d6c..261748c 100644 ---

[PATCH 23/52] drm/amd/powerplay: init hwmgr for ELM/BAF

From: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index

[PATCH 22/52] drm/amd/powerplay: enable dpm for baffin.

From: Rex Zhu Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile |3 +- .../amd/powerplay/hwmgr/ellesmere_dyn_defaults.h | 62 + .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c | 4560

[PATCH 21/52] drm/amd/powerplay: add smu support for ellesmere/baffin

From: rezhu Signed-off-by: Rex Zhu Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c| 11 +- drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +- .../drm/amd/powerplay/smumgr/ellesmere_smumgr.c| 969 +

[PATCH 20/52] drm/amd/powerplay: add header files for ellesmere smu manager.

From: rezhu Signed-off-by: Rex Zhu --- .../gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h| 401 + .../gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h | 10088 +++ drivers/gpu/drm/amd/powerplay/inc/smu74.h | 774 ++

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