Hi Heiko.
On Mon, Dec 09, 2019 at 03:42:07PM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner
>
> The XPP055C272 is a 5.5" 720x1280 DSI display.
Can we get the size info included in the title in the binding?
Then all relavant info is in the binding, and no git digging is needed.
>
> Signed
https://bugzilla.kernel.org/show_bug.cgi?id=205853
--- Comment #3 from Janpieter Sollie (janpieter.sol...@dommel.be) ---
the issue seems to be in the DC driver: booting the amdgpu kernel module with
"dc=0" reduces the output to:
[7.050414] amdgpu :0a:00.0: [drm:amd
Hi Heiko.
On Mon, Dec 09, 2019 at 03:42:06PM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner
>
> Shenzhen Xinpeng Technology Co., Ltd produces for example display panels.
>
> Signed-off-by: Heiko Stuebner
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file cha
https://bugzilla.kernel.org/show_bug.cgi?id=205853
--- Comment #2 from Janpieter Sollie (janpieter.sol...@dommel.be) ---
Created attachment 286281
--> https://bugzilla.kernel.org/attachment.cgi?id=286281&action=edit
kernel config file
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--- Comment #1 from Janpieter Sollie (janpieter.sol...@dommel.be) ---
Created attachment 286279
--> https://bugzilla.kernel.org/attachment.cgi?id=286279&action=edit
lspci -v output
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https://bugzilla.kernel.org/show_bug.cgi?id=205853
Bug ID: 205853
Summary: amdgpu kernel bug: kernel null pointer dereference
Product: Drivers
Version: 2.5
Kernel Version: 5.4.2
Hardware: x86-64
OS: Linux
Tree
Currently, the interrupt lines requested by Panfrost
use unmeaningful names, which adds some obscurity
to interrupt introspection (i.e. any tool based
on procfs' interrupts file).
In order to improve this, prefix each requested
interrupt with the module name: panfrost-{gpu,job,mmu}.
Signed-off-by
Add tracking of pages that were pinned via FOLL_PIN.
As mentioned in the FOLL_PIN documentation, callers who effectively set
FOLL_PIN are required to ultimately free such pages via unpin_user_page().
The effect is similar to FOLL_GET, and may be thought of as "FOLL_GET
for DIO and/or RDMA use".
P
Hi,
On Fri, Dec 13, 2019 at 4:07 PM Daniel Vetter wrote:
>
> On Fri, Dec 13, 2019 at 03:45:30PM -0800, Douglas Anderson wrote:
> > The bridge chip supports these DP rates according to TI's spec:
> > * 1.62 Gbps (RBR)
> > * 2.16 Gbps
> > * 2.43 Gbps
> > * 2.7 Gbps (HBR)
> > * 3.24 Gbps
> > * 4.32
On Fri, Dec 13, 2019 at 5:24 PM Niranjan Vishwanathapura <
niranjana.vishwanathap...@intel.com> wrote:
> On Fri, Dec 13, 2019 at 04:58:42PM -0600, Jason Ekstrand wrote:
> >
> > +/**
> > + * struct drm_i915_gem_vm_bind
> > + *
> > + * Bind an object in a vm's page table.
> >
> > F
On Mon, Nov 25, 2019 at 10:43:54AM +0100, Daniel Vetter wrote:
> I'll add more fancy logic to them soon, so everyone really has to use
> them. Plus they already provide some nice additional debug
> infrastructure on top of direct ww_mutex usage for the fences tracked
> by dma_resv.
>
> Aside: We m
I'll add more fancy logic to them soon, so everyone really has to use
them. Plus they already provide some nice additional debug
infrastructure on top of direct ww_mutex usage for the fences tracked
by dma_resv.
v2: Fix the lost _interruptible (Michael)
Signed-off-by: Daniel Vetter
Cc: Lucas Sta
On Fri, Dec 13, 2019 at 03:45:30PM -0800, Douglas Anderson wrote:
> The bridge chip supports these DP rates according to TI's spec:
> * 1.62 Gbps (RBR)
> * 2.16 Gbps
> * 2.43 Gbps
> * 2.7 Gbps (HBR)
> * 3.24 Gbps
> * 4.32 Gbps
> * 5.4 Gbps (HBR2)
>
> As far as I can tell, only RBR, HBR, and HBR2 a
https://bugzilla.kernel.org/show_bug.cgi?id=204987
--- Comment #2 from Frank Steinborn (stei...@nognu.de) ---
Still happens on 5.4.2.
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On Fri, Dec 13, 2019 at 10:52:03PM +, Li, Juston wrote:
> On Fri, 2019-12-13 at 23:36 +0200, Ville Syrjälä wrote:
> > On Thu, Oct 03, 2019 at 11:31:25AM -0700, Juston Li wrote:
> > > From: Daniel Stone
> > >
> > > getfb2 allows us to pass multiple planes and modifiers, just like
> > > addfb2
https://bugzilla.kernel.org/show_bug.cgi?id=204987
Frank Steinborn (stei...@nognu.de) changed:
What|Removed |Added
Summary|general protection fault in |fault in
The bridge chip supports these DP rates according to TI's spec:
* 1.62 Gbps (RBR)
* 2.16 Gbps
* 2.43 Gbps
* 2.7 Gbps (HBR)
* 3.24 Gbps
* 4.32 Gbps
* 5.4 Gbps (HBR2)
As far as I can tell, only RBR, HBR, and HBR2 are part of the DP spec.
If other rates work then I believe it's because the sink has a
If we fail training at a lower DP link rate let's now keep trying
until we run out of rates to try. Basically the algorithm here is to
start at the link rate that is the theoretical minimum and then slowly
bump up until we run out of rates or hit the max rate of the sink. We
query the sink using
At least one panel hooked up to the bridge (AUO B116XAK01) only
supports 1 lane of DP. Let's read this information and stop
hardcoding 4 DP lanes.
Signed-off-by: Douglas Anderson
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 32 +--
1 file changed, 30 insertions(+), 2 del
The driver used to say that the value to program into bridge register
0x93 was dp_lanes - 1. Looking at the datasheet for the bridge, this
is wrong. The data sheet says:
* 1 = 1 lane
* 2 = 2 lanes
* 3 = 4 lanes
A more proper way to express this encoding is min(dp_lanes, 3).
At the moment this c
The ti-sn65dsi86 is a bridge from MIPI to DP and thus has two links:
the MIPI link and the DP link. The two links do not need to have the
same format or number of lanes. Stop using MIPI variables when
talking about the DP link.
This has zero functional change because:
* currently we are hardcodi
When we iterate over ti_sn_bridge_dp_rate_lut, there's no reason to
start at index 0 which always contains the value 0. 0 is not a valid
link rate.
This change should have no real effect but is a small cleanup.
Signed-off-by: Douglas Anderson
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +-
This series contains a pile of patches that was created to support
hooking up the AUO B116XAK01 panel to the eDP side of the bridge. In
general it should be useful for hooking up a wider variety of DP
panels to the bridge, especially those with lower resolution and lower
bits per pixel.
The overa
We'll re-organize the ti_sn_bridge_enable() function a bit to group
together all the parts relating to link training and split them into a
sub-function. This is not intended to have any functional change and
is in preparation for trying link training several times at different
rates. One small si
The current bridge driver always forced us to use 24 bits per pixel
over the DP link. This is a waste if you are hooked up to a panel
that only supports 6 bits per color or fewer, since in that case you
ran run at 18 bits per pixel and thus end up at a lower DP clock rate.
Let's support this.
Wh
These two things were in one function. Split into two. This looks
like it's duplicating some code, but don't worry. This is is just in
preparation for future changes.
This is intended to have zero functional change and will just make
future patches easier to understand.
Signed-off-by: Douglas
On Mon, Dec 02, 2019 at 09:33:59PM +0200, Adrian Ratiu wrote:
> This provides an example DT binding for the MIPI DSI host controller
> present on the i.MX6 SoC based on Synopsis DesignWare v1.01 IP.
>
> Cc: Rob Herring
> Cc: Neil Armstrong
> Signed-off-by: Sjoerd Simons
> Signed-off-by: Martyn
On Thu, Nov 07, 2019 at 04:24:13PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
Annoyingly __drm_atomic_helper_crtc_reset() does two
totally separate things:
a) reset the state to defaults values
b) assign the crtc->state pointer
I just want a) without the b) so let's split out part
a) into
On Fri, Dec 13, 2019 at 6:30 PM Robert Jarzmik wrote:
> Daniel Thompson writes:
> >
> > ... I worry that palmtc.c is no longer compilable for some configs.
> I you're right, there is a very simple way to test it :
> make pxa_defconfig && make -j
>
> It should scream if the compilation is broken,
On Fri, Dec 13, 2019 at 6:24 PM Robert Jarzmik wrote:
> Linus Walleij writes:
> > On Sun, Dec 8, 2019 at 9:06 PM Robert Jarzmik
> > wrote:
> >> Linus Walleij writes:
> > So it will theoretically "spi0.1"
> >
> > Beware about bugs in the above interpreter because it is
> > just my brain.
>
> W
On Mon, Dec 02, 2019 at 04:41:22PM +0100, Paul Cercueil wrote:
> Add bindings documentation for the Frida 3.5" (320x240 pixels) 24-bit
> TFT LCD panel.
>
> v2: Switch documentation from plain text to YAML
>
> Signed-off-by: Paul Cercueil
> ---
> .../display/panel/frida,frd350h54004.yaml | 3
On Mon, 2 Dec 2019 16:41:21 +0100, Paul Cercueil wrote:
> Add an entry for Shenzhen Frida LCD Co., Ltd.
>
> v2: No change
>
> Signed-off-by: Paul Cercueil
> Acked-by: Sam Ravnborg
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acke
On Fri, Dec 13, 2019 at 04:58:42PM -0600, Jason Ekstrand wrote:
+/**
+ * struct drm_i915_gem_vm_bind
+ *
+ * Bind an object in a vm's page table.
First off, this is something I've wanted for a while for Vulkan, it's just
never made its way high enough up the priority list.
The pull request you sent on Fri, 13 Dec 2019 17:04:44 +1000:
> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2019-12-13
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/b2cb931d724b08def6e833541a37b08ebd59ab43
Thank you!
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On Fri, Dec 13, 2019 at 4:07 PM Niranjana Vishwanathapura <
niranjana.vishwanathap...@intel.com> wrote:
> Shared Virtual Memory (SVM) runtime allocator support allows
> binding a shared virtual address to a buffer object (BO) in the
> device page table through an ioctl call.
>
> Cc: Joonas Lahtine
On Mon, Dec 02, 2019 at 01:47:45PM +, Chandan Uddaraju wrote:
> Add bindings for Snapdragon 845 DisplayPort and
> display-port PLL driver.
Is it just me, but I keep getting 2 copies of codeaurora emails?
>
> Changes in V2:
> Provide details about sel-gpio
This is V3, what changed in V3?
>
On Fri, 2019-12-13 at 23:36 +0200, Ville Syrjälä wrote:
> On Thu, Oct 03, 2019 at 11:31:25AM -0700, Juston Li wrote:
> > From: Daniel Stone
> >
> > getfb2 allows us to pass multiple planes and modifiers, just like
> > addfb2
> > over addfb.
> >
> > Changes since v1:
> > - unused modifiers set t
Hi Hsin-Yi and Nicolas,
Thank you for the patch.
On Wed, Dec 11, 2019 at 02:19:09PM +0800, Hsin-Yi Wang wrote:
> From: Nicolas Boichat
>
> ANX7688 is a HDMI to DP converter (as well as USB-C port controller),
> that has an internal microcontroller.
>
> The only reason a Linux kernel driver is
Hi Hsin-Yi and Nicolas,
Thank you for the patch.
On Wed, Dec 11, 2019 at 02:19:11PM +0800, Hsin-Yi Wang wrote:
> From: Nicolas Boichat
>
> This driver supports single input, 2 output display mux (e.g.
> HDMI mux), that provide its status via a GPIO.
>
> Signed-off-by: Nicolas Boichat
> Signed
Hi Fabrizio,
Thank you for the patch.
On Fri, Dec 06, 2019 at 04:32:53PM +, Fabrizio Castro wrote:
> Add binding for the idk-2121wr LVDS panel from Advantech.
>
> Some panel-specific documentation can be found here:
> https://buy.advantech.eu/Displays/Embedded-LCD-Kits-High-Brightness/model-
For Shared Virtual Memory (SVM) system (SYS) allocator, there is no
backing buffer object (BO). Add support to bind a VA to PA mapping
in the device page table.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/d
Use blitter engine to copy pages during migration.
As blitter context virtual address space is shared with other flows,
ensure virtual address are allocated properly from that address space.
Also ensure completion of blitter copy by waiting on the fence of the
issued request.
Cc: Joonas Lahtinen
Add support to dump page table for debug purpose.
Here is an example dump. Format is,
[] :
Page Table dump start 0x0 len 0x
[0x0fe] 0x7f000: 0x6b0003
[0x1e6] 0x7f798: 0x6c0003
[0x16d] 0x7f79ada00: 0x5f0003
Add support function to blitter copy SVM VAs without requiring any
gem objects. Also add function to wait for completion of the copy.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/Makefile
Plugin device memory through HMM as DEVICE_PRIVATE.
Add support functions to allocate pages and free pages from device memory.
Implement ioctl to prefetch pages from host to device memory.
For now, only support migrating pages from host memory to device memory.
Cc: Joonas Lahtinen
Cc: Jon Bloomfi
Copy the pages duing SVM migration using memcpy().
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/i915_svm_devmem.c | 72 ++
1 file changed, 72 insertions(+)
diff --git a/driv
From: Venkata Sandeep Dhanalakota
As PCIe is non-coherent link, do not allow direct access to buffer
objects across the PCIe link for SVM case. Upon CPU accesses (mmap, pread),
migrate buffer object to host memory.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Cc:
Add SVM as a capability and allow user to enable/disable SVM
functionality on a per context basis.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Venkata Sandeep Dhanalakota
---
drivers/gpu/drm/i915/gem/i915_g
Add Shared Virtual Memory (SVM) support information.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
Documentation/gpu/i915.rst | 29 +
1 file changed, 29 insertions(+)
diff --git a/Documentati
Shared Virtual Memory (SVM) runtime allocator support allows
binding a shared virtual address to a buffer object (BO) in the
device page table through an ioctl call.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/
Use HMM page table mirroring support to build device page table.
Implement the bind ioctl and bind the process address range in the
specified context's ppgtt.
Handle invalidation notifications by unbinding the address range.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Du
Shared Virtual Memory (SVM) allows the programmer to use a single virtual
address space which will be shared between threads executing on CPUs and GPUs.
It abstracts away from the user the location of the backing memory, and hence
simplifies the user programming model.
SVM supports two types of vir
As PCIe is non-coherent link, do not allow direct memory access across
PCIe link. Handle CPU fault by migrating pages back to host memory.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/i915_svm_devme
On Wed, Dec 11, 2019 at 12:19 AM Hsin-Yi Wang wrote:
>
> From: Nicolas Boichat
>
> Add bindings for Generic GPIO mux driver.
>
> Signed-off-by: Nicolas Boichat
> Signed-off-by: Hsin-Yi Wang
> ---
> Change from RFC to v1:
> - txt to yaml
> ---
> .../bindings/display/bridge/gpio-mux.yaml | 8
On Fri, Nov 29, 2019 at 12:25:44PM +0530, Harigovindan P wrote:
> Add a compatible string to support sc7180 panel version.
>
> Signed-off-by: Harigovindan P
> ---
> .../bindings/display/visionox,rm69299.txt | 68
> ++
> 1 file changed, 68 insertions(+)
> create mod
On Fri, Dec 13, 2019 at 12:08 PM Daniel Vetter wrote:
>
> On Mon, Nov 25, 2019 at 10:43:55AM +0100, Daniel Vetter wrote:
> > I'll add more fancy logic to them soon, so everyone really has to use
> > them. Plus they already provide some nice additional debug
> > infrastructure on top of direct ww_m
Hi Fabrizio,
Thank you for the patch.
On Fri, Dec 06, 2019 at 04:32:52PM +, Fabrizio Castro wrote:
> Primary and companion encoders need to set the same mode for
> things to work properly.
>
> rcar_lvds_mode_set gets called into for the primary encoder only,
> therefore initialize the compan
Hi Fabrizio,
Thank you for the patch.
On Fri, Dec 06, 2019 at 04:32:51PM +, Fabrizio Castro wrote:
> DT properties dual-lvds-even-pixels and dual-lvds-odd-pixels
> can be used to work out if the driver needs to swap even
> and odd pixels around.
>
> This patch makes use of the return value f
On Fri, Dec 13, 2019 at 12:10 PM Daniel Vetter wrote:
>
> On Mon, Nov 25, 2019 at 10:43:56AM +0100, Daniel Vetter wrote:
> > I'll add more fancy logic to them soon, so everyone really has to use
> > them. Plus they already provide some nice additional debug
> > infrastructure on top of direct ww_m
On Thu, Oct 03, 2019 at 11:31:25AM -0700, Juston Li wrote:
> From: Daniel Stone
>
> getfb2 allows us to pass multiple planes and modifiers, just like addfb2
> over addfb.
>
> Changes since v1:
> - unused modifiers set to 0 instead of DRM_FORMAT_MOD_INVALID
> - update ioctl number
>
> Signed-o
Hi Fabrizio,
Thank you for the patch.
On Fri, Dec 06, 2019 at 04:32:50PM +, Fabrizio Castro wrote:
> For dual-LVDS configurations, it is now possible to mark the
> DT port nodes for the sink with boolean properties (like
> dual-lvds-even-pixels and dual-lvds-odd-pixels) to let drivers
> know
Hi Fabrizio,
Thank you for the patch.
On Fri, Dec 06, 2019 at 04:32:49PM +, Fabrizio Castro wrote:
> Dual-LVDS panels are mistakenly identified as bridges, this
> commit replaces the current logic with a call to
> drm_of_find_panel_or_bridge to sort that out.
>
> Signed-off-by: Fabrizio Cast
Hi Fabrizio,
Thank you for the patch.
On Fri, Dec 06, 2019 at 04:32:48PM +, Fabrizio Castro wrote:
> An LVDS dual-link connection is made of two links, with even
> pixels transitting on one link, and odd pixels on the other
> link. The device tree can be used to fully describe dual-link
> LVD
These are updates to devidce drivers and file systems that for some
reason or another were not included in the kernel in the previous
y2038 series.
I've gone through all users of time_t again to make sure the
kernel is in a long-term maintainable state.
Posting these as a series for better organi
The timespec structure and associated interfaces are deprecated and will
be removed in the future because of the y2038 overflow.
The use of ktime_to_timespec() in timeout_to_jiffies() does not
suffer from that overflow, but is easy to avoid by just converting
the ktime_t into jiffies directly.
Re
Most kernel interfaces that take a timespec require normalized
representation with tv_nsec between 0 and NSEC_PER_SEC.
Passing values larger than 0x1ull further behaves differently
on 32-bit and 64-bit kernels, and can cause the latter to spend a long
time counting seconds in timespec64_su
struct timespec is being removed from the kernel because it often leads
to code that is not y2038-safe.
In the etnaviv driver, monotonic timestamps are used, which do not suffer
from overflow, but the usage of timespec here gets in the way of removing
the interface completely.
Pass down the user-
>-Original Message-
>From: dri-devel On Behalf Of
>Daniel Vetter
>Sent: Friday, December 13, 2019 3:08 PM
>To: DRI Development
>Cc: Daniel Vetter ; Intel Graphics Development
>; etna...@lists.freedesktop.org; Russell
>King ; Vetter, Daniel
>
>Subject: Re: [PATCH 1/4] drm/etnaviv: Use dma_
From: Mikita Lipski
[why]
Since for DSC MST connector's PBN is claculated differently
due to compression, we have to recalculate both PBN and
VCPI slots for that connector.
[how]
The function iterates through all the active streams to
find, which have DSC enabled, then recalculates PBN for
it an
From: David Francis
During MST mode enumeration, if a new dc_sink is created,
populate it with dsc caps as appropriate.
Use drm_dp_mst_dsc_aux_for_port to get the raw caps,
then parse them onto dc_sink with dc_dsc_parse_dsc_dpcd.
Reviewed-by: Wenjing Liu
Signed-off-by: David Francis
Signed-of
On Fri, Dec 13, 2019 at 01:17:59PM +0200, Tomi Valkeinen wrote:
> Hi Daniel,
>
> On 13/12/2019 12:30, Daniel Vetter wrote:
>
> > > +DRM DRIVERS FOR TI KEYSTONE
> > > +M: Jyri Sarha
> > > +M: Tomi Valkeinen
> > > +L: dri-devel@lists.freedesktop.org
> > > +S: Maintained
>
On Mon, Nov 25, 2019 at 10:43:56AM +0100, Daniel Vetter wrote:
> I'll add more fancy logic to them soon, so everyone really has to use
> them. Plus they already provide some nice additional debug
> infrastructure on top of direct ww_mutex usage for the fences tracked
> by dma_resv.
>
> Signed-off-
From: David Francis
For DSC MST, sometimes monitors would break out
in full-screen static. The issue traced back to the
PPS generation code, where these variables were being used
uninitialized and were picking up garbage.
memset to 0 to avoid this
Reviewed-by: Nicholas Kazlauskas
Signed-off-by
From: David Francis
Add drm_dp_mst_dsc_aux_for_port. To enable DSC, the DSC_ENABLED
register might have to be written on the leaf port's DPCD,
its parent's DPCD, or the MST manager's DPCD. This function
finds the correct aux for the job.
As part of this, add drm_dp_mst_is_virtual_dpcd. Virtual D
From: Mikita Lipski
[why]
Whenever a connector on an MST network is changed or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if that stre
From: Mikita Lipski
Whenever a connector on an MST network is attached, detached, or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if tha
From: David Francis
If there is limited link bandwidth on a MST network,
it must be divided fairly between the streams on that network
Implement an algorithm to determine the correct DSC config
for each stream
The algorithm:
This
[ ] ( )
represents the range of b
From: Mikita Lipski
Adding a helper function to be called by
drivers outside of DRM to enable DSC on
the MST ports.
Function is called to recalculate VCPI allocation
if DSC is enabled and raise the DSC flag to enable.
In case of disabling DSC the flag is set to false
and recalculation of VCPI sl
From: David Francis
Instead of having drm_dp_dpcd_read/write and
drm_dp_mst_dpcd_read/write as entry points into the
aux code, have drm_dp_dpcd_read/write handle both.
This means that DRM drivers can make MST DPCD read/writes.
v2: Fix spacing
v3: Dump dpcd access on MST read/writes
v4: Fix call
From: David Francis
As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating
if FEC can be supported up to that point in the MST network.
The bit is the first byte of the ENUM_PATH_RESOURCES ack reply,
bottom-most bit (refer to section 2.11.9.4 of DP standard,
v1.4)
That value is needed for FE
From: Mikita Lipski
[why]
Adding PBN attribute to drm_dp_vcpi_allocation structure to
keep track of how much bandwidth each Port requires.
Adding drm_dp_mst_atomic_check_bw_limit to verify that
state's bandwidth needs doesn't exceed available bandwidth.
The funtion is called in drm_dp_mst_atomic_
From: Mikita Lipski
[why]
For DSC case we cannot use topology manager's PBN divider
variable. The default divider does not take FEC into account.
Therefore the driver has to calculate its own divider based
on the link rate and lane count its handling, as it is hw specific.
[how]
Pass pbn_div as
From: Mikita Lipski
[why]
drm_dp_mst_atomic_check_topology_state() should be renamed
to reflect more specific type of check. Since it is verifying
payload allocation limit it should be renamed into
drm_dp_mst_atomic_check_vcpi_alloc_limit()
Cc: Lyude Paul
Signed-off-by: Mikita Lipski
---
driv
From: Mikita Lipski
[why]
Need to calculate VCPI slots differently for DSC
to take in account current link rate, link count
and FEC.
[how]
Add helper to get pbn_div from dc_link
Cc: Harry Wentland
Cc: Lyude Paul
Signed-off-by: Mikita Lipski
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst
From: Mikita Lipski
This set of patches is a continuation of DSC enablement
patches for AMDGPU. This set enables DSC on MST. It also
contains implementation of both encoder and connector
atomic check routines.
These patches have been introduced in multiple
iterations to the mailing list before.
From: Mikita Lipski
Synaptics DP1.4 hubs (BRANCH_ID 0x90CC24) do not
support virtual DPCD registers, but do support DSC.
The DSC caps can be read from the physical aux,
like in SST DSC. These hubs have many different
DEVICE_IDs. Add a new quirk to detect this case.
v2: Fix error when checking r
From: David Francis
With DSC, bpp can be fractional in multiples of 1/16.
Change drm_dp_calc_pbn_mode to reflect this, adding a new
parameter bool dsc. When this parameter is true, treat the
bpp parameter as having units not of bits per pixel, but
1/16 of a bit per pixel
v2: Don't add separate
From: David Francis
This field on drm_dp_mst_branch was never filled
It is initialized to zero when the port is kzallocced.
When a port is added to the list, increment num_ports,
and when a port is removed from the list, decrement num_ports.
v2: remember to decrement on port removal
v3: don't e
From: David Francis
Rework the dm_helpers_write_dsc_enable callback to
handle the MST case.
Use the cached dsc_aux field.
Reviewed-by: Wenjing Liu
Signed-off-by: David Francis
Signed-off-by: Mikita Lipski
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 ++-
1 file cha
On Mon, Nov 25, 2019 at 10:43:53AM +0100, Daniel Vetter wrote:
> I'll add more fancy logic to them soon, so everyone really has to use
> them. Plus they already provide some nice additional debug
> infrastructure on top of direct ww_mutex usage for the fences tracked
> by dma_resv.
>
> Signed-off-
On Mon, Nov 25, 2019 at 10:43:55AM +0100, Daniel Vetter wrote:
> I'll add more fancy logic to them soon, so everyone really has to use
> them. Plus they already provide some nice additional debug
> infrastructure on top of direct ww_mutex usage for the fences tracked
> by dma_resv.
>
> Signed-off-
Hi Daniel.
On Fri, Dec 13, 2019 at 06:26:05PM +0100, Daniel Vetter wrote:
> Checking both is one too much, so wrap a WARN_ON around it to stope
> the copypasta.
>
> Signed-off-by: Daniel Vetter
> Cc: Sam Ravnborg
> Cc: Boris Brezillon
> Cc: Nicolas Ferre
> Cc: Alexandre Belloni
> Cc: Ludovic
I'm just going to put Chia's review comment here since it sums
the issue rather nicely:
"(1) Semantically, a dma-buf is in DMA domain. CPU access from the
importer must be surrounded by {begin,end}_cpu_access. This gives the
exporter a chance to move the buffer to the CPU domain temporarily.
(2
On Fri, Dec 13, 2019 at 03:59:02PM +0530, Ramalingam C wrote:
> On 2019-12-12 at 14:02:20 -0500, Sean Paul wrote:
> > From: Sean Paul
> >
> > On HDCP disable, clear the repeater bit. This ensures if we connect a
> > non-repeater sink after a repeater, the bit is in the state we expect.
> >
> > F
On Fri, Dec 13, 2019 at 04:40:33PM +0530, Ramalingam C wrote:
> On 2019-12-12 at 14:02:25 -0500, Sean Paul wrote:
> > From: Sean Paul
> >
> > This patch adds some protection against connectors being destroyed
> > before the HDCP workers are finished.
> >
> > For check_work, we do a synchronous c
On Fri, Dec 13, 2019 at 05:28:25PM +0530, Ramalingam C wrote:
> On 2019-12-12 at 14:02:26 -0500, Sean Paul wrote:
> > From: Sean Paul
> >
> > This patch is required for HDCP over MST. If a port is being used for
> > multiple HDCP streams, we don't want to fully disable HDCP on a port if
> > one o
On Fri, Dec 13, 2019 at 11:54:36AM -0500, Steven Rostedt wrote:
> On Fri, 13 Dec 2019 11:47:03 -0500
> Sean Paul wrote:
>
> > > Why is there a separate trace event for each of these?
> > >
> >
> > To make it easier on userspace to enable just a single drm category.
> >
>
> But trace events
Hi Jerry.
Thanks!
On Thu, Dec 12, 2019 at 07:52:08PM +0800, Jerry Han wrote:
> Support Boe Himax8279d 8.0" 1200x1920 TFT LCD panel, it is a MIPI DSI
> panel.
>
> V11:
> - Use the backlight support in drm_panel to simplify the driver (Sam)
...
> - Support Boe Himax8279d 8.0" 1200x1920 TFT LCD pa
Hi Miquel,
Am Freitag, 13. Dezember 2019, 19:10:49 CET schrieb Miquel Raynal:
> Add the display subsystem routes with the two available CRTCs: vopb
> and vopl (big and little). For each CRTC, add the LVDS endpoints. MIPI
> DSI endpoints will come later.
>
> Signed-off-by: Miquel Raynal
> ---
>
The R-Car LVDS encoder driver implements the bridge .mode_set()
operation for the sole purpose of storing the mode in the LVDS private
data, to be used later when enabling the encoder.
Switch to the bridge .atomic_enable() and .atomic_disable() operations
in order to access the global atomic state
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