On Mon, 14 Mar 2022 12:53:24 +0100, Julia Lawall wrote:
> Various spelling mistakes in comments.
> Detected with the help of Coccinelle.
>
Applied to 5.18/scsi-queue, thanks!
[02/30] scsi: lpfc: fix typos in comments
https://git.kernel.org/mkp/scsi/c/9a866e6aaf4e
[17/30] scsi: elx: libe
Hi,
On Fri, Mar 18, 2022 at 4:27 PM Stephen Boyd wrote:
>
> > > Pushing hpd state checking into aux
> > > transactions looks like the wrong direction. Also, as I said up above I
> > > am concerned that even checking the GPIO won't work and we need some way
> > > to ask the bridge if HPD is assert
From: Sujaritha Sundaresan
Throttling here refers to the GT frequency being clipped. Each of
the throttle reason attributes will have a 0 or 1 value depending
upon whether there is throttling and also the specific reason for
it.
The following is a brief description of the sysfs throttle
frequenc
Now tiles have their own sysfs interfaces under the gt/
directory. Because RPS is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.../card0
├── gt
│ ├──
Now tiles have their own sysfs interfaces under the gt/
directory. Because RC6 is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.../card0
├── gt
│ ├──
Now that we have tiles we want each of them to have its own
interface. A directory "gt/" is created under "cardN/" that will
contain as many diroctories as the tiles.
In the coming patches tile related interfaces will be added. For
now the sysfs gt structure simply has an id interface related
to t
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four GTs are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source compatibility
with legacy driver paths. A for_each
Hi,
This is the second series that prepares i915 to host multitile
platforms. It introduces the for_each_gt() macro that loops over
the tiles to perform per gt actions.
This patch is a combination of two patches developed originally
by Abdiel, who introduced some refactoring during probe, and the
The "gt_is_root(struct intel_gt *gt)" helper return true if the
gt is the root gt, which means that its id is 0. Return false
otherwise.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/intel_gt.h | 5
With the upcoming multitile support each tile will have its own
local memory. Mark the current LMEM with the suffix '0' to
emphasise that it belongs to the root tile.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
---
drivers/
Arghhh Sorry for spamming! I sent the wrong series!
Please ignore this.
Andi
On Sat, Mar 19, 2022 at 12:46:33AM +0200, Andi Shyti wrote:
> Hi,
>
> This is the second series that prepares i915 to host multitile
> platforms. It introduces the for_each_gt() macro that loops over
> the tiles to
Quoting Doug Anderson (2022-03-18 14:58:55)
> Hi,
>
> On Fri, Mar 18, 2022 at 1:17 PM Stephen Boyd wrote:
> >
> > > > > + ret = dp_catalog_aux_wait_for_hpd_connect_state(aux->catalog);
> > > >
> > > > Why are we making aux transactions when hpd isn't asserted? Can we only
> > > > register th
From: Sujaritha Sundaresan
This patch adds the following new sysfs frequency attributes:
- punit_req_freq_mhz
- throttle_reason_status
- throttle_reason_pl1
- throttle_reason_pl2
- throttle_reason_pl4
- throttle_reason_thermal
- throttle_re
Now tiles have their own sysfs interfaces under the gt/
directory. Because RPS is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.../card0
├── gt
│ ├──
Now tiles have their own sysfs interfaces under the gt/
directory. Because RC6 is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.../card0
├── gt
│ ├──
Now that we have tiles we want each of them to have its own
interface. A directory "gt/" is created under "cardN/" that will
contain as many diroctories as the tiles.
In the coming patches tile related interfaces will be added. For
now the sysfs gt structure simply has an id interface related
to t
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four GTs are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source compatibility
with legacy driver paths. A for_each
The "gt_is_root(struct intel_gt *gt)" helper return true if the
gt is the root gt, which means that its id is 0. Return false
otherwise.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/intel_gt.h | 5
With the upcoming multitile support each tile will have its own
local memory. Mark the current LMEM with the suffix '0' to
emphasise that it belongs to the root tile.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
---
drivers/
Hi,
This is the second series that prepares i915 to host multitile
platforms. It introduces the for_each_gt() macro that loops over
the tiles to perform per gt actions.
This patch is a combination of two patches developed originally
by Abdiel, who introduced some refactoring during probe, and the
On Sat, 19 Mar 2022 at 04:11, Lyude Paul wrote:
>
> Whoops, sorry! I was unsure of the preference in name we should go with so I
> poked Ben on the side to ask them, but I can see they haven't yet responded.
> I'll poke thme again and see if I can get a response.
Yeah, please keep _prom as opposed
Hi,
On Fri, Mar 18, 2022 at 1:17 PM Stephen Boyd wrote:
>
> > > > + ret = dp_catalog_aux_wait_for_hpd_connect_state(aux->catalog);
> > >
> > > Why are we making aux transactions when hpd isn't asserted? Can we only
> > > register the aux device once we know that state is "connected"? I'm
>
Hi Zack-
> On Mar 18, 2022, at 1:43 PM, Zack Rusin wrote:
>
> From: Zack Rusin
>
> vmw_move assumed that buffers to be moved would always be
> vmw_buffer_object's but after introduction of new placement for mob
> pages that's no longer the case.
> The resulting invalid read didn't have any pr
Hi Dave, Daniel,
Fixes for 5.18.
The following changes since commit f6d790e5a7fe42706756c7fa1686d08d230610fc:
Merge tag 'drm-intel-next-fixes-2022-03-10' of
git://anongit.freedesktop.org/drm/drm-intel into drm-next (2022-03-11 13:27:00
+1000)
are available in the Git repository at:
https
Quoting Doug Anderson (2022-03-18 09:24:17)
> Hi,
>
> On Thu, Mar 17, 2022 at 6:19 PM Stephen Boyd wrote:
> >
> > Quoting Sankeerth Billakanti (2022-03-16 10:35:51)
> > > The source device should ensure the sink is ready before
> > > proceeding to read the sink capability or performing any
On 2022-03-18 13:22, Rob Clark wrote:
On Fri, Mar 18, 2022 at 9:27 AM Andrey Grodzovsky
wrote:
On 2022-03-18 12:20, Rob Clark wrote:
On Fri, Mar 18, 2022 at 9:04 AM Andrey Grodzovsky
wrote:
On 2022-03-17 16:35, Rob Clark wrote:
On Thu, Mar 17, 2022 at 12:50 PM Andrey Grodzovsky
wrote:
when allocating a resource in place it is common to free the buffer's
resource, then allocate a new resource in a different placement.
e.g. amdgpu_bo_create_kernel_at calls ttm_resource_free, then calls
ttm_bo_mem_space.
In this situation, bo->resource will be null as it is cleared during
the ini
The pull request you sent on Fri, 18 Mar 2022 13:50:16 +1000:
> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2022-03-18
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/cced5148a1303a2ec57d04a7745a560821b45280
Thank you!
--
Deet-doot-dot, I am a bot.
https://k
Hi
Am 18.03.22 um 01:50 schrieb Chuansheng Liu:
Easily hit the below list corruption:
==
list_add corruption. prev->next should be next (c0ceb090), but
was ec604507edc8. (prev=ec604507edc8).
WARNING: CPU: 65 PID: 3959 at lib/list_debug.c:26
__list_add_valid+0x53/0x80
CPU: 65 PID:
The chip is capable of swapping DPI RGB channels. The driver currently
does not implement support for this functionality. Write the MIPI_PN_SWAP
register to 0 to assure the color swap is disabled.
Acked-by: Maxime Ripard
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Maxime Ripard
Cc: Robert Fo
Read out the Vendor/Chip/Version ID registers from the chip before
performing any configuration, and validate that the registers have
correct values. This is mostly a simple test whether DSI register
access does work, since that tends to be broken on various bridges.
Acked-by: Maxime Ripard
Signe
The chip contains fractional PLL, however the driver currently hard-codes
one specific PLL setting. Implement generic PLL parameter calculation code,
so any DPI panel with arbitrary pixel clock can be attached to this bridge.
The datasheet for this bridge is not available, the PLL behavior has bee
Rename and inline macro ICN6211_DSI() into function chipone_writeb()
to keep all function names lower-case. No functional change.
Acked-by: Maxime Ripard
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Maxime Ripard
Cc: Robert Foss
Cc: Sam Ravnborg
Cc: Thomas Zimmermann
To: dri-devel@lists.fr
The ICN6211 chip starts in I2C configuration mode after cold boot.
Implement support for configuring the chip via I2C in addition to
the current DSI LP command mode configuration support. The later
seems to be available only on chips which have additional MCU on
the panel/bridge board which preconf
Implement .atomic_get_input_bus_fmts callback, which sets up the
input (DSI-end) format, and that format can then be used in pipeline
format negotiation between the DSI-end of this bridge and the other
component closer to the scanout engine.
Acked-by: Maxime Ripard
Signed-off-by: Marek Vasut
Cc:
The DSI burst mode is more energy efficient than the DSI sync pulse mode,
make use of the burst mode since the chip supports it as well. Disable the
generation of EoT packet, the chip ignores it, so no point in emitting it.
Enable transmission of data in LP mode, otherwise register read via DSI
doe
Both example code [1], [2] as well as one provided by custom panel vendor
set register SYS_CTRL_1 to 0x88. What exactly does the value mean is unknown
due to unavailable datasheet. Align this register value with example code.
[1]
https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/
The chip register layout has nothing to do with MIPI DCS, the registers
incorrectly marked as MIPI DCS in the driver are regular chip registers
often with completely different function.
Fill in the actual register names and bits from [1] and [2] and add the
entire register layout, since the docume
The HFP_HSW_HBP_HI register must be programmed with 2 LSbits of each
Horizontal Front Porch/Sync/Back Porch. Currently the driver programs
this register to 0, which breaks displays with either value above 255.
The HFP_MIN register must be set to the same value as HFP_LI, otherwise
there is visible
The driver currently hard-codes HS/VS polarity to active-low and DE to
active-high, which is not correct for a lot of supported DPI panels.
Add the missing mode flag handling for HS/VS/DE polarity.
Acked-by: Maxime Ripard
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Maxime Ripard
Cc: Robert F
This series fixes multiple problems with the ICN6211 driver and adds
support for configuration of the chip via I2C bus.
First, in the current state, the ICN6211 driver hard-codes DPI timing
and clock settings specific to some unknown panel. The settings provided
by panel driver are ignored. Using
From: Fei Yang
GPU hangs have been observed when multiple engines write to the
same aux_inv register at the same time. To avoid this each engine
should only invalidate its own auxiliary table. The function
gen12_emit_flush_xcs() currently invalidate the auxiliary table for
all engines because the
>> static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
>> {
>> *cs++ = MI_LOAD_REGISTER_IMM(1);
>> @@ -296,7 +272,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32
>> mode)
>> if (!HAS_FLAT_CCS(rq->engine->i915)) {
>> aux_inv
Maybe also good to add dri-devel to these discussions.
I'm not sure where exactly we landed with dgpu error capture (maybe I
should check the code but it's really w/e here), but I think we can
also toss in "you need a non-recoverable context for error capture to
work on dgpu". Since that simplifie
Whoops, sorry! I was unsure of the preference in name we should go with so I
poked Ben on the side to ask them, but I can see they haven't yet responded.
I'll poke thme again and see if I can get a response.
On Fri, 2022-03-18 at 10:55 +0100, Christophe Leroy wrote:
> Hi Paul,
>
> Le 05/03/2022 à
On Fri, 18 Mar 2022 at 17:16, Maxime Ripard wrote:
>
> On Fri, Mar 18, 2022 at 05:05:11PM +, Dave Stevenson wrote:
> > Hi Maxime
> >
> > On Fri, 18 Mar 2022 at 16:35, Maxime Ripard wrote:
> > >
> > > On Mon, Mar 07, 2022 at 04:26:56PM +0100, Max Krummenacher wrote:
> > > > On Wed, Mar 2, 2022
From: Zack Rusin
The res is initialized here only if there's no errors so passing it to
ttm_resource_fini in the error paths results in a kernel oops. In the
error paths, instead of the unitialized res, we have to use to use
node->base on which ttm_resource_init was called.
Sample affected backt
From: Zack Rusin
The kms code wasn't validating the modifiers and was letting through
unsupported formats. rgb8 was never properly supported and has no
matching svga screen target format so remove it.
This fixes format/modifier failures in kms_addfb_basic from IGT.
Signed-off-by: Zack Rusin
Rev
From: Zack Rusin
With very limited vram on svga3 it's difficult to handle all the surface
migrations. Without gbobjects, i.e. the ability to store surfaces in
guest mobs, there's no reason to support intermediate svga2 features,
especially because we can fall back to fb traces and svga3 will neve
From: Zack Rusin
Writes to SVGA_REG_CURSOR_MOBID did not wait for the buffers to be fully
populated. This sometimes results in the device not being aware of
the buffer when the cursor mob register was written.
Properly wait for the buffer to be fully populated before setting it
as a cursor mob.
From: Zack Rusin
vmw_move assumed that buffers to be moved would always be
vmw_buffer_object's but after introduction of new placement for mob
pages that's no longer the case.
The resulting invalid read didn't have any practical consequences
because the memory isn't used unless the object actuall
From: Zack Rusin
This is a set of various smaller fixes. The 5th, drm/ttm one needs to be
looked at by Christian, especially because it's a kernel oops. The others
are largely trivial vmwgfx fixes.
Zack Rusin (5):
drm/vmwgfx: Fix an invalid read
drm/vmwgfx: Fix mob cursor allocation race
d
Hi Daniel,
On 3/17/22 19:36, Daniel Dadap wrote:
>
> On 3/17/22 11:42, Hans de Goede wrote:
>> Hi Daniel,
>>
>> On 3/17/22 14:28, Daniel Dadap wrote:
On Mar 17, 2022, at 07:17, Hans de Goede wrote:
Hi,
> On 3/16/22 21:33, Daniel Dadap wrote:
> Some notebook systems w
On Thu, Feb 17, 2022 at 05:15:15PM +, Chery, Nanley G wrote:
> > >> [...]
> > >> --- a/include/uapi/drm/drm_fourcc.h
> > >> +++ b/include/uapi/drm/drm_fourcc.h
> > >> @@ -583,6 +583,28 @@ extern "C" {
> > >>*/
> > >> #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
> > >>
Hi,
On Wed, Mar 16, 2022 at 10:36 AM Sankeerth Billakanti
wrote:
>
> Enable support for eDP interface via aux_bus on CRD platform.
>
> Signed-off-by: Sankeerth Billakanti
> ---
>
> Changes in v5:
> - Change the order of patches
> - Remove the backlight nodes
> - Remove the bias setting
>
On Fri, Mar 18, 2022 at 9:27 AM Andrey Grodzovsky
wrote:
>
>
> On 2022-03-18 12:20, Rob Clark wrote:
> > On Fri, Mar 18, 2022 at 9:04 AM Andrey Grodzovsky
> > wrote:
> >>
> >> On 2022-03-17 16:35, Rob Clark wrote:
> >>> On Thu, Mar 17, 2022 at 12:50 PM Andrey Grodzovsky
> >>> wrote:
> On 20
On Fri, Mar 18, 2022 at 05:05:11PM +, Dave Stevenson wrote:
> Hi Maxime
>
> On Fri, 18 Mar 2022 at 16:35, Maxime Ripard wrote:
> >
> > On Mon, Mar 07, 2022 at 04:26:56PM +0100, Max Krummenacher wrote:
> > > On Wed, Mar 2, 2022 at 5:22 PM Marek Vasut wrote:
> > > >
> > > > On 3/2/22 15:21, Ma
Ping, could someone review and/or pick this up? This is going to break a
few builds with CONFIG_WERROR, it would be nice to have it in
drm-misc-next-fixes, as the commit it is fixing is in drm-misc-next.
Cheers,
Nathan
On Wed, Mar 02, 2022 at 04:59:09PM -0700, Nathan Chancellor wrote:
> Clang war
On 3/18/22 17:47, Steven Price wrote:
> On 18/03/2022 14:41, Dmitry Osipenko wrote:
>>
>> On 3/17/22 02:04, Dmitry Osipenko wrote:
>>>
>>> On 3/16/22 18:04, Steven Price wrote:
On 14/03/2022 22:42, Dmitry Osipenko wrote:
> Replace Panfrost's memory shrinker with a generic DRM memory shrink
Hi Maxime
On Fri, 18 Mar 2022 at 16:35, Maxime Ripard wrote:
>
> On Mon, Mar 07, 2022 at 04:26:56PM +0100, Max Krummenacher wrote:
> > On Wed, Mar 2, 2022 at 5:22 PM Marek Vasut wrote:
> > >
> > > On 3/2/22 15:21, Maxime Ripard wrote:
> > > > Hi,
> > >
> > > Hi,
> > >
> > > > Please try to avoid
On Mon, Mar 07, 2022 at 04:26:56PM +0100, Max Krummenacher wrote:
> On Wed, Mar 2, 2022 at 5:22 PM Marek Vasut wrote:
> >
> > On 3/2/22 15:21, Maxime Ripard wrote:
> > > Hi,
> >
> > Hi,
> >
> > > Please try to avoid top posting
> Sorry.
>
> > >
> > > On Wed, Feb 23, 2022 at 04:25:19PM +0100, Max
On 2022-03-18 12:20, Rob Clark wrote:
On Fri, Mar 18, 2022 at 9:04 AM Andrey Grodzovsky
wrote:
On 2022-03-17 16:35, Rob Clark wrote:
On Thu, Mar 17, 2022 at 12:50 PM Andrey Grodzovsky
wrote:
On 2022-03-17 14:25, Rob Clark wrote:
On Thu, Mar 17, 2022 at 11:10 AM Andrey Grodzovsky
wrote:
Hi,
On Thu, Mar 17, 2022 at 6:19 PM Stephen Boyd wrote:
>
> Quoting Sankeerth Billakanti (2022-03-16 10:35:51)
> > The source device should ensure the sink is ready before
> > proceeding to read the sink capability or performing any aux transactions.
> > The sink will indicate its readine
On Fri, Mar 18, 2022 at 9:04 AM Andrey Grodzovsky
wrote:
>
>
> On 2022-03-17 16:35, Rob Clark wrote:
> > On Thu, Mar 17, 2022 at 12:50 PM Andrey Grodzovsky
> > wrote:
> >>
> >> On 2022-03-17 14:25, Rob Clark wrote:
> >>> On Thu, Mar 17, 2022 at 11:10 AM Andrey Grodzovsky
> >>> wrote:
> On 2
On Fri, Mar 18, 2022 at 05:02:49PM +0100, Paul Kocialkowski wrote:
> While bridge/panel detection was initially relying on the usual
> port/ports-based of graph detection, it was recently changed to
> perform the lookup on any child node that is not port/ports
> instead when such a node is availabl
Hi Paul,
On Wed, Mar 9, 2022 at 8:02 PM Paul Kocialkowski
wrote:
>
> While bridge/panel detection was initially relying on the usual
> port/ports-based of graph detection, it was recently changed to
> perform the lookup on any child node that is not port/ports
> instead when such a node is availa
On 2022-03-17 16:35, Rob Clark wrote:
On Thu, Mar 17, 2022 at 12:50 PM Andrey Grodzovsky
wrote:
On 2022-03-17 14:25, Rob Clark wrote:
On Thu, Mar 17, 2022 at 11:10 AM Andrey Grodzovsky
wrote:
On 2022-03-17 13:35, Rob Clark wrote:
On Thu, Mar 17, 2022 at 9:45 AM Christian König
wrote:
A
On Wed, Mar 16, 2022 at 04:40:49PM +0100, Paul Kocialkowski wrote:
> Hi Maxime,
>
> Thanks for the review!
>
> On Thu 10 Mar 22, 15:54, Maxime Ripard wrote:
> > Hi Paul,
> >
> > On Wed, Mar 09, 2022 at 03:32:00PM +0100, Paul Kocialkowski wrote:
> > > While bridge/panel detection was initially re
On Fri, Mar 18, 2022 at 12:42 AM Christian König
wrote:
>
> Am 17.03.22 um 18:31 schrieb Rob Clark:
> > On Thu, Mar 17, 2022 at 10:27 AM Daniel Vetter wrote:
> >> [SNIP]
> >>> (At some point, I'd like to use scheduler for the replay, and actually
> >>> use drm_sched_stop()/etc.. but last time I l
On Fri, Mar 18, 2022 at 12:19 AM Dan Carpenter wrote:
>
> On Thu, Mar 17, 2022 at 08:03:59AM -0700, Rob Clark wrote:
> > > > diff --git a/drivers/gpu/drm/msm/msm_gpu.c
> > > > b/drivers/gpu/drm/msm/msm_gpu.c
> > > > index 4ec62b601adc..68f3f8ade76d 100644
> > > > --- a/drivers/gpu/drm/msm/msm_gpu
On 18.03.2022 03:10, Andi Shyti wrote:
Now that we have tiles we want each of them to have its own
interface. A directory "gt/" is created under "cardN/" that will
contain as many diroctories as the tiles.
In the coming patches tile related interfaces will be added. For
now the sysfs gt structur
On 18.03.2022 03:10, Andi Shyti wrote:
Now tiles have their own sysfs interfaces under the gt/
directory. Because RPS is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.
Am 2022-03-18 um 08:38 schrieb Christian König:
Am 17.03.22 um 20:11 schrieb Felix Kuehling:
Am 2022-03-17 um 04:21 schrieb Christian König:
Am 17.03.22 um 01:20 schrieb Felix Kuehling:
Let amdgpu_vm_handle_moved update all BO VA mappings of BOs
reserved by
the caller. This will be useful fo
On 18/03/2022 14:41, Dmitry Osipenko wrote:
>
> On 3/17/22 02:04, Dmitry Osipenko wrote:
>>
>> On 3/16/22 18:04, Steven Price wrote:
>>> On 14/03/2022 22:42, Dmitry Osipenko wrote:
Replace Panfrost's memory shrinker with a generic DRM memory shrinker.
Signed-off-by: Dmitry Osipenko
On 3/17/22 02:04, Dmitry Osipenko wrote:
>
> On 3/16/22 18:04, Steven Price wrote:
>> On 14/03/2022 22:42, Dmitry Osipenko wrote:
>>> Replace Panfrost's memory shrinker with a generic DRM memory shrinker.
>>>
>>> Signed-off-by: Dmitry Osipenko
>>> ---
>> I gave this a spin on my Firefly-RK3288
On 18/03/2022 05:26, fei.y...@intel.com wrote:
From: Fei Yang
GPU hangs have been observed when multiple engines write to the
same aux_inv register at the same time. To avoid this each engine
should only invalidate its own auxiliary table. The function
gen12_emit_flush_xcs() currently invalid
On Fri, Mar 18, 2022 at 03:21:45PM +0100, Maxime Ripard wrote:
> On Fri, Mar 18, 2022 at 03:42:48PM +0200, Andy Shevchenko wrote:
> > On Thu, Mar 17, 2022 at 12:39:57PM +0100, Javier Martinez Canillas wrote:
> > > On 3/17/22 09:18, Geert Uytterhoeven wrote:
> >
> > > By the way, you should probabl
On Fri, Mar 18, 2022 at 03:42:48PM +0200, Andy Shevchenko wrote:
> On Thu, Mar 17, 2022 at 12:39:57PM +0100, Javier Martinez Canillas wrote:
> > On 3/17/22 09:18, Geert Uytterhoeven wrote:
>
> > By the way, you should probably request commit access to the drm-misc tree:
> >
> > https://drm.pages.
On Fri, Mar 18, 2022 at 01:19:18PM +, Matthew Auld wrote:
> On 18/03/2022 02:10, Andi Shyti wrote:
> > Now that we have tiles we want each of them to have its own
> > interface. A directory "gt/" is created under "cardN/" that will
> > contain as many diroctories as the tiles.
> >
> > In the c
On Thu, Mar 17, 2022 at 12:39:57PM +0100, Javier Martinez Canillas wrote:
> On 3/17/22 09:18, Geert Uytterhoeven wrote:
> By the way, you should probably request commit access to the drm-misc tree:
>
> https://drm.pages.freedesktop.org/maintainer-tools/commit-access.html
Does it really work? I t
On 18/03/2022 02:10, Andi Shyti wrote:
Now that we have tiles we want each of them to have its own
interface. A directory "gt/" is created under "cardN/" that will
contain as many diroctories as the tiles.
In the coming patches tile related interfaces will be added. For
now the sysfs gt structur
On 18.03.2022 03:10, Andi Shyti wrote:
From: Sujaritha Sundaresan
This patch adds the following new sysfs frequency attributes:
- punit_req_freq_mhz
- throttle_reason_status
- throttle_reason_pl1
- throttle_reason_pl2
- throttle_reason_pl4
- thro
On 18.03.2022 03:10, Andi Shyti wrote:
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four GTs are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source compatibi
Am 17.03.22 um 20:11 schrieb Felix Kuehling:
Am 2022-03-17 um 04:21 schrieb Christian König:
Am 17.03.22 um 01:20 schrieb Felix Kuehling:
Let amdgpu_vm_handle_moved update all BO VA mappings of BOs reserved by
the caller. This will be useful for handling extra BO VA mappings in
KFD VMs that ar
On Fri, 4 Mar 2022 at 15:18, Dave Stevenson
wrote:
>
> Hi All
A gentle ping on this series. Any comments on the approach?
Thanks.
> Changes from v1:
> - New patch to refactor drm_bridge_chain_post_disable and
> drm_bridge_chain_pre_enable
> to reuse drm_atomic_bridge_chain_post_disable /
> d
On Thu, Mar 17, 2022 at 06:52:28PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 17, 2022 at 06:33:53PM +0200, Stanislav Lisovskiy wrote:
> > Whenever we are not able to get enough timeslots
> > for required PBN, let's try to allocate those
> > using DSC, just same way as we do for SST.
> >
> > Those
Il 11/03/22 10:34, Ricardo Cañuelo ha scritto:
When unbinding a DRM master driver there's a race condition that
sometimes results in an invalid vm access when userspace (gnome-shell)
issues a DRM_IOCTL_MODE_GETCONNECTOR ioctl right after a bridge has been
removed from an encoder's bridge chain.
On 18/03/2022 09:38, Lionel Landwerlin wrote:
Hey Matthew, all,
This sounds like a good thing to have.
There are a number of DG2 machines where we have a small BAR and this is
causing more apps to fail.
Anv currently reports 3 memory heaps to the app :
- local device only (not host visi
Il 11/03/22 10:34, Ricardo Cañuelo ha scritto:
Depending on the bridge code, certain userspace events during a driver
teardown (such as a DRM ioctl call) might cause a race condition where
the drm_bridge_chain_pre_enable() and drm_bridge_chain_post_enable()
functions could be called for a bridge
On Thu, Mar 17, 2022 at 11:55:37PM +0100, Daniel Mack wrote:
> If the optional regulator lookup fails, reset the pointer to NULL.
> Other functions such as mipi_dbi_poweron_reset_conditional() only do
> a NULL pointer check and will otherwise dereference the error pointer.
>
> Fixes: 5a04227326b04
Hi Paul,
Le 05/03/2022 à 10:51, Christophe Leroy a écrit :
Le 05/03/2022 à 08:38, Christophe Leroy a écrit :
Le 04/03/2022 à 21:24, Lyude Paul a écrit :
This mostly looks good to me. Just one question (and one comment down
below
that needs addressing). Is this with ppc32? (I ask because pp
Hey Matthew, all,
This sounds like a good thing to have.
There are a number of DG2 machines where we have a small BAR and this is
causing more apps to fail.
Anv currently reports 3 memory heaps to the app :
- local device only (not host visible) -> mapped to lmem
- device/cpu -> mappe
On Thu, 2022-03-17 at 18:58 +0100, José Expósito wrote:
> The function "drm_of_find_panel_or_bridge" has been deprecated in
> favor of "devm_drm_of_get_bridge".
>
> Switch to the new function and reduce boilerplate.
>
> Signed-off-by: José Expósito
>
> ---
>
> v2: (Thanks to Liu Ying)
>
> -
Hi Andy,
On Thu, Mar 17, 2022 at 03:23:12PM +0800, Andy Yan wrote:
>I found a obvious error in 0x604(OVERLAY_LAYER_SEL) register, the
>configuration value
>
>is 0x54763513.
>
>I am not sure if you know clearly about this register:
>
>Every four bits of this register select
On 16/03/2022 14:57, Nicolas Belin wrote:
Adding the audio support on the HDMI bridge for I2S only.
Signed-off-by: Nicolas Belin
Signed-off-by: Andy.Hsieh
---
drivers/gpu/drm/bridge/ite-it66121.c | 627 +++
1 file changed, 627 insertions(+)
diff --git a/drivers/gpu/
On 16/03/2022 14:57, Nicolas Belin wrote:
Set the register page length or window length to
0x100 according to the documentation.
Fixes: 988156dc2fc9 ("drm: bridge: add it66121 driver")
Signed-off-by: Nicolas Belin
---
drivers/gpu/drm/bridge/ite-it66121.c | 2 +-
1 file changed, 1 insertion(+
On Fri, Feb 18, 2022 at 11:57 PM Harry Wentland wrote:
>
> On 2022-02-18 07:12, Simon Ser wrote:
> > On Friday, February 18th, 2022 at 12:54, Hans de Goede
> > wrote:
> >
> >> On 2/18/22 12:39, Simon Ser wrote:
> >>> On Friday, February 18th, 2022 at 11:38, Hans de Goede
> >>> wrote:
> >>>
> >
Init panel orientation property after connector is initialized. Let the
panel driver decides the orientation value later.
Signed-off-by: Hsin-Yi Wang
---
drivers/gpu/drm/msm/dsi/dsi_manager.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
b/drivers
krane, kakadu, and kodama boards have a default panel rotation.
Signed-off-by: Hsin-Yi Wang
Reviewed-by: Enric Balletbo i Serra
Tested-by: Enric Balletbo i Serra
---
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/
Init panel orientation property after connector is initialized. Let the
panel driver decides the orientation value later.
Signed-off-by: Hsin-Yi Wang
Acked-by: Chun-Kuang Hu
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/mediate
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