Missing 'static inline'. Will be fixed in next rev.
Am 23.02.23 um 20:01 schrieb kernel test robot:
Hi Thomas,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[cannot apply to drm-misc/drm-misc-next v6.2 v6.2-rc8 v6.2-rc7 next-20230223
> -Original Message-
> From: Nilawar, Badal
> Sent: Friday, February 24, 2023 12:12 AM
> To: intel-...@lists.freedesktop.org
> Cc: Gupta, Anshuman ; Ewins, Jon
> ; Belgaumkar, Vinay ;
> Vivi, Rodrigo ; Roper, Matthew D
> ; dri-devel@lists.freedesktop.org
> Subject: [PATCH] drm/i915/mtl:
Hi Mikhail,
this is pretty clearly a problem with the system and/or it's BIOS and
not the GPU hw or the driver.
The option pci=nocrs makes the kernel ignore additional resource windows
the BIOS reports through ACPI. This then most likely leads to problems
with amdgpu because it can't bring u
On Thu, 2023-02-23 at 20:02 +0100, Werner Sembach wrote:
>
> Am 23.02.23 um 19:56 schrieb Werner Sembach:
> >
> > Am 23.02.23 um 19:26 schrieb Hogander, Jouni:
> > > On Wed, 2023-02-22 at 15:17 +0100, Werner Sembach wrote:
> > > > On these Barebones PSR 2 is recognized as supported but is very
>
Hi,
a gentle ping
Best regards,
Alexander
Am Mittwoch, 25. Januar 2023, 15:52:15 CET schrieb Alexander Stein:
> From: Markus Niebel
>
> The DE signal is active high on this display, fill in the missing
> bus_flags. This aligns panel_desc with its display_timing.
>
> Fixes: 9a2654c0f62a ("drm/
On Fri, 2023-02-24 at 11:29 +0800, Meng Tang wrote:
>
>
> On 2023/2/24 11:13, Zack Rusin wrote:
> >
> > That's correct. That's the way this works. The ioctl is allocating a buffer,
> > there's
> > no infinite space for buffers on a system and, given that your app just
> > allocates
> > and never
On Fri, 2023-02-24 at 10:46 +0800, Meng Tang wrote:
> On 2023/2/23 20:50, Zack Rusin wrote:
> > On Thu, 2023-02-23 at 15:04 +0800, Meng Tang wrote:
> > > A privilege escalation vulnerability was found in vmwgfx driver
> > > in drivers/gpu/drm/vmwgfx/vmwgfx_drv.c in GPU component of Linux
> > > kern
On 2023/2/23 22:07, Thomas Zimmermann wrote:
It's the same story all over: you rather want to remove all these
lookup helpers and do a single test before you create the modesetting
pipeline:
if (chip == LS7A2000 && index == 0)
lscd_create_output_ls7a2000_0();
else if (chip == LS7A200
No functional modification involved.
drivers/gpu/drm/gma500/cdv_device.c:218 cdv_errata() warn: inconsistent
indenting.
Reported-by: Abaci Robot
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4126
Signed-off-by: Jiapeng Chong
---
Changes in v2:
-Change the subject.
drivers/gpu/drm/gm
MTL's primary GT can continue to use the same engine TLB invalidation
programming as past Xe_HP-based platforms. However the media GT needs
some special handling:
* Invalidation registers on the media GT are singleton registers
(unlike the primary GT where they are still MCR).
* Since the GSC
The Driver-FLR flow may inadvertently exit early before the full
completion of the re-init of the internal HW state if we only poll
GU_DEBUG Bit31 (polling for it to toggle from 0 -> 1). Instead
we need a two-step completion wait-for-completion flow that also
involves GU_CNTL. See the patch and new
Thanks Daniele, you are right about the fixes tag - i totally forgot that MTL
is still force-probe.
Will respin with the bit definition fix, remove the fixes-tag and leave out the
get/put runtime-pm from rev3 (as per your comment on rev3).
Rev4 coming right up.
...alan
P.S. I had the same thoug
On 2/22/2023 1:01 PM, Alan Previn wrote:
The Driver-FLR flow may inadvertently exit early before the full
completion of the re-init of the internal HW state if we only poll
GU_DEBUG Bit31 (polling for it to toggle from 0 -> 1). Instead
we need a two-step completion wait-for-completion flow tha
Hi,
I have a laptop ASUS ROG Strix G15 Advantage Edition G513QY-HQ007. But
it is impossible to use without AC power because the system losts nvme
when I disconnect the power adapter.
Messages from kernel log when it happens:
nvme nvme0: controller is down; will reset: CSTS=0x, PCI_STATUS=0
On 2/23/2023 2:04 PM, Alan Previn wrote:
The Driver-FLR flow may inadvertently exit early before the full
completion of the re-init of the internal HW state if we only poll
GU_DEBUG Bit31 (polling for it to toggle from 0 -> 1). Instead
we need a two-step completion wait-for-completion flow tha
On Fri, 2023-02-17 at 03:12 +, Teres Alexis, Alan Previn wrote:
> On Tue, 2023-02-14 at 13:38 -0800, Teres Alexis, Alan Previn wrote:
> > Add MTL's function for ARB session creation using PXP firmware
> > version 4.3 ABI structure format.
>
> alan:snip
>
> Not part of this patch today but a n
On Tue, 2023-02-14 at 13:38 -0800, Teres Alexis, Alan Previn wrote:
> Add MTL's function for ARB session creation using PXP firmware
> version 4.3 ABI structure format.
>
alan:snip
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index aecc65b5da70
On 2/23/2023 2:08 PM, Dmitry Baryshkov wrote:
Hi Abhinav,
On Thu, 23 Feb 2023 at 21:17, Abhinav Kumar wrote:
Hi Dmitry
On 2/23/2023 1:57 AM, Dmitry Baryshkov wrote:
The rewritten dpu_hw_ctl_setup_blendstage() can lightly smash the stack
when setting the SSPP_NONE pipe. However it was unn
Hi Abhinav,
On Thu, 23 Feb 2023 at 21:17, Abhinav Kumar wrote:
>
> Hi Dmitry
>
> On 2/23/2023 1:57 AM, Dmitry Baryshkov wrote:
> > The rewritten dpu_hw_ctl_setup_blendstage() can lightly smash the stack
> > when setting the SSPP_NONE pipe. However it was unnoticed until the
> > kernel was tested
The Driver-FLR flow may inadvertently exit early before the full
completion of the re-init of the internal HW state if we only poll
GU_DEBUG Bit31 (polling for it to toggle from 0 -> 1). Instead
we need a two-step completion wait-for-completion flow that also
involves GU_CNTL. See the patch and new
On Wed, 2023-02-22 at 13:01 -0800, Teres Alexis, Alan Previn wrote:
> The Driver-FLR flow may inadvertently exit early before the full
> completion of the re-init of the internal HW state if we only poll
> GU_DEBUG Bit31 (polling for it to toggle from 0 -> 1). Instead
> we need a two-step completio
On 22.02.2023 18:04, Peter Zijlstra wrote:
On Wed, Jan 18, 2023 at 04:35:22PM +0100, Andrzej Hajda wrote:
Andrzej Hajda (7):
arch: rename all internal names __xchg to __arch_xchg
linux/include: add non-atomic version of xchg
arch/*/uprobes: simplify arch_uretprobe_hijack_return_addr
Hi Thomas,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[cannot apply to drm-misc/drm-misc-next v6.2 v6.2-rc8 v6.2-rc7 next-20230223
v6.2 next-20230223]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
On Fri, Feb 24, 2023 at 12:11:40AM +0530, Badal Nilawar wrote:
> Apply Wa_14017073508 for MTL SoC die A step instead of graphics step.
> To get the SoC die stepping there is no direct interface so using
> revid as revid 0 aligns with SoC die A step.
>
> Bspec: 55420
This doesn't prove anything. I
Hi Thomas,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[cannot apply to drm-misc/drm-misc-next v6.2 v6.2-rc8 v6.2-rc7 next-20230223
v6.2 next-20230223]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
Hi Dmitry
On 2/23/2023 1:57 AM, Dmitry Baryshkov wrote:
The rewritten dpu_hw_ctl_setup_blendstage() can lightly smash the stack
when setting the SSPP_NONE pipe. However it was unnoticed until the
kernel was tested under AOSP (with some kind of stack protection/check).
This fixes the following b
* Danilo Krummrich [230222 13:13]:
> On 2/21/23 19:20, Liam R. Howlett wrote:
> > * Danilo Krummrich [230217 08:45]:
> > > Add infrastructure to keep track of GPU virtual address (VA) mappings
> > > with a decicated VA space manager implementation.
> > >
> > > New UAPIs, motivated by Vulkan spar
Hi Thomas,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[cannot apply to drm-misc/drm-misc-next v6.2 v6.2-rc8 v6.2-rc7 next-20230223
v6.2 next-20230223]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting
Am 23.02.23 um 19:56 schrieb Werner Sembach:
Am 23.02.23 um 19:26 schrieb Hogander, Jouni:
On Wed, 2023-02-22 at 15:17 +0100, Werner Sembach wrote:
On these Barebones PSR 2 is recognized as supported but is very
buggy:
- Upper third of screen does sometimes not updated, resulting in
disappea
Am 23.02.23 um 19:56 schrieb Werner Sembach:
Am 23.02.23 um 19:26 schrieb Hogander, Jouni:
On Wed, 2023-02-22 at 15:17 +0100, Werner Sembach wrote:
On these Barebones PSR 2 is recognized as supported but is very
buggy:
- Upper third of screen does sometimes not updated, resulting in
disappea
Am 23.02.23 um 19:26 schrieb Hogander, Jouni:
On Wed, 2023-02-22 at 15:17 +0100, Werner Sembach wrote:
On these Barebones PSR 2 is recognized as supported but is very
buggy:
- Upper third of screen does sometimes not updated, resulting in
disappearing cursors or ghosts of already closed Window
On Thu, Feb 23, 2023 at 1:38 AM Pekka Paalanen wrote:
>
> On Wed, 22 Feb 2023 07:37:26 -0800
> Rob Clark wrote:
>
> > On Wed, Feb 22, 2023 at 1:49 AM Pekka Paalanen wrote:
> > >
> > > On Tue, 21 Feb 2023 09:53:56 -0800
> > > Rob Clark wrote:
> > >
> > > > On Tue, Feb 21, 2023 at 8:48 AM Luben T
On Thu, Feb 23, 2023 at 10:03 AM Thomas Hellström
wrote:
>
> Hi, Daniel,
>
> On 2/16/23 21:18, Daniel Vetter wrote:
> > On Thu, Feb 16, 2023 at 05:27:28PM +0100, Thomas Hellström wrote:
> >> A slightly unusual cover letter for a single patch.
> >>
> >> The page table walker is currently used by th
Hi Maarten,
On Thu, Feb 23, 2023 at 07:25:23PM +0100, Maarten Lankhorst wrote:
> Hi Dave and Daniel,
>
> Here's the first pull request for v6.4-rc1.
>
> Enjoy!
>
> ~Maarten
>
> drm-misc-next-2023-02-23:
> drm-misc-next for v6.4-rc1:
>
> First pull request to keep the delta from growing too bi
Apply Wa_14017073508 for MTL SoC die A step instead of graphics step.
To get the SoC die stepping there is no direct interface so using
revid as revid 0 aligns with SoC die A step.
Bspec: 55420
Fixes: 8f70f1ec587d ("drm/i915/mtl: Add Wa_14017073508 for SAMedia")
Signed-off-by: Badal Nilawar
---
On Thu, 23 Feb 2023 at 15:27, Dmitry Baryshkov
wrote:
>
> The rewritten dpu_hw_ctl_setup_blendstage() can lightly smash the stack
> when setting the SSPP_NONE pipe. However it was unnoticed until the
> kernel was tested under AOSP (with some kind of stack protection/check).
>
> This fixes the foll
On Wed, 2023-02-22 at 15:17 +0100, Werner Sembach wrote:
> On these Barebones PSR 2 is recognized as supported but is very
> buggy:
> - Upper third of screen does sometimes not updated, resulting in
> disappearing cursors or ghosts of already closed Windows saying
> behind.
> - Approximately 40 px
Hi Dave and Daniel,
Here's the first pull request for v6.4-rc1.
Enjoy!
~Maarten
drm-misc-next-2023-02-23:
drm-misc-next for v6.4-rc1:
First pull request to keep the delta from growing too big.
UAPI Changes:
- Convert rockchip bindings to YAML.
- Constify kobj_type structure in dma-buf.
- FBD
The GSC FW load is a slow process (up to 250 ms), so we defer it to a
dedicated worker to avoid stalling the init flow for that long. However,
we currently start this worker before the HW init is complete, so there
is a chance that the GSC loading code submits to the HW before the
engine initializa
A couple of fixes for issue related to synchronization of the GSC worker
start/end with kernel init/fini and suspend/resume. See the individual
commit messages for details.
Note: not fixes tag since MTL is still under force probe
Cc: Alan Previn
Daniele Ceraolo Spurio (2):
drm/i915/gsc: flush
If we unload the driver and wedge before the GSC worker is complete,
the worker will hit an error on its submission to the GSC engine and
then exit. This is hard to hit for a user, but it is reproducible
with skipping selftests. The error is handled gracefully by the
worker, so there are no functio
On 2/23/23 17:22, Christian König wrote:
Am 23.02.23 um 15:29 schrieb Thomas Hellström:
On 2/23/23 12:15, Christian König wrote:
Am 23.02.23 um 11:57 schrieb Thomas Hellström:
From: Maarten Lankhorst
Now that we have a generic suballocation helper, Use it in amdgpu.
For lines that get mov
Hi Thierry, Daniel, and David,
On Fri, Jan 27, 2023 at 11:14:00PM +0100, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> The error handling for platform_get_irq() failing no longer
> works after a recent change, clang now points this out with
> a warning:
>
> drivers/gpu/host1x/dev.c:520:6: erro
Am 23.02.23 um 15:29 schrieb Thomas Hellström:
On 2/23/23 12:15, Christian König wrote:
Am 23.02.23 um 11:57 schrieb Thomas Hellström:
From: Maarten Lankhorst
Now that we have a generic suballocation helper, Use it in amdgpu.
For lines that get moved or changed, also fix up pre-existing styl
On 23/02/2023 12:51, Konrad Dybcio wrote:
This is a partial merge of [1], subject to be dropped if a header
update is executed.
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21484
Suggested-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a2xx
On 23/02/2023 12:51, Konrad Dybcio wrote:
This is a partial merge of [1], subject to be dropped if a header
update is executed.
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21480/
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a2xx.xml.h | 6 ++
1 file chan
On Thu, 23 Feb 2023 at 15:57, Sankeerth Billakanti
wrote:
>
> The DP driver resources are currently enabled and disabled directly based on
> code flow.
> As mentioned in bug 230631602, we want to do the following:
private bug tracker
>
> 1) Refactor the dp/edp parsing code to move it to probe (
Hi, Daniel,
On 2/16/23 21:18, Daniel Vetter wrote:
On Thu, Feb 16, 2023 at 05:27:28PM +0100, Thomas Hellström wrote:
A slightly unusual cover letter for a single patch.
The page table walker is currently used by the xe driver only,
but the code is generic so we can be good citizens and add it
On 2/23/23 08:06, Christian König wrote:
Am 22.02.23 um 17:40 schrieb Danilo Krummrich:
On 2/22/23 16:14, Christian König wrote:
Am 22.02.23 um 16:07 schrieb Danilo Krummrich:
On 2/22/23 11:25, Christian König wrote:
Am 17.02.23 um 14:44 schrieb Danilo Krummrich:
+/**
+ * DOC: Overview
+
On Thu, 23 Feb 2023 at 15:57, Sankeerth Billakanti
wrote:
>
> The eDP panel is identified and enumerated during probe of the panel-edp
> driver. The current DP driver triggers this panel-edp driver probe while
> getting the panel-bridge associated with the eDP panel from the platform
> driver bind
From: Maarten Lankhorst
Use the generic suballocation helper for radeon.
v3:
- Select the suballoc helper in Kconfig (Thomas).
Signed-off-by: Maarten Lankhorst
Co-developed-by: Thomas Hellström
Signed-off-by: Thomas Hellström
Reviewed-by: Christian König
---
drivers/gpu/drm/radeon/Kconfig
From: Maarten Lankhorst
Now that we have a generic suballocation helper, Use it in amdgpu.
For lines that get moved or changed, also fix up pre-existing style issues.
Signed-off-by: Maarten Lankhorst
Co-developed-by: Thomas Hellström
Signed-off-by: Thomas Hellström
Reviewed-by: Christian Köni
From: Maarten Lankhorst
Suballocating a buffer object is something that is not driver-specific
and useful for many drivers.
Use a slightly modified version of amdgpu_sa.c
v2:
- Style cleanups.
- Added / Modified documentation.
- Use u64 for the sizes and offset. The code dates back to 2012 and
This series (or at least the suballocator helper) is a prerequisite
for the new Xe driver.
There was an unresolved issue when the series was last up for review,
and that was the per allocation aligment. Last message was from
Maarten Lankhorst arguing that the larger per-driver alignment used
would
On 23.02.2023 15:48, Dmitry Baryshkov wrote:
> On Thu, 23 Feb 2023 at 15:49, Konrad Dybcio wrote:
>>
>>
>>
>> On 23.02.2023 14:06, Dmitry Baryshkov wrote:
>>> On Thu, 23 Feb 2023 at 14:07, Konrad Dybcio
>>> wrote:
According to the vendor sources, it's equal to 16, which makes hbb_lo
On Thu, 23 Feb 2023 at 15:49, Konrad Dybcio wrote:
>
>
>
> On 23.02.2023 14:06, Dmitry Baryshkov wrote:
> > On Thu, 23 Feb 2023 at 14:07, Konrad Dybcio
> > wrote:
> >>
> >> According to the vendor sources, it's equal to 16, which makes hbb_lo
> >> equal to 3.
> >
> > I think we might be stricken
On 23.02.2023 15:43, Dmitry Baryshkov wrote:
> On Thu, 23 Feb 2023 at 14:06, Konrad Dybcio wrote:
>>
>> Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
>> but don't implement the associated GMUs. This is due to the fact that
>> the GMU directly pokes at RPMh. Sadly, this me
On Thu, 23 Feb 2023 at 14:06, Konrad Dybcio wrote:
>
> Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
> but don't implement the associated GMUs. This is due to the fact that
> the GMU directly pokes at RPMh. Sadly, this means we have to take care
> of enabling & scaling power
This patch doesn't apply. Please make sure you are using drm-next or
linux-next.
Alex
On Fri, Feb 17, 2023 at 1:15 PM Arthur Grillo wrote:
>
> Make implicit enum conversion to avoid -Wenum-conversion warning, such
> as:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.
Applied. Thanks.
On Fri, Feb 17, 2023 at 1:15 PM Arthur Grillo wrote:
>
> Remove local variables that were just set but were never used. This
> decrease the number of -Wunused-but-set-variable warnings.
>
> Signed-off-by: Arthur Grillo
> ---
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_en
Applied. Thanks.
On Fri, Feb 17, 2023 at 1:15 PM Arthur Grillo wrote:
>
> Remove a couple of local variables that are only set but never used,
> also remove an static utility function that is never used in consequence
> of the variable removal.
>
> This decrease the number of -Wunused-but-set-va
On 2/23/23 12:15, Christian König wrote:
Am 23.02.23 um 11:57 schrieb Thomas Hellström:
From: Maarten Lankhorst
Now that we have a generic suballocation helper, Use it in amdgpu.
For lines that get moved or changed, also fix up pre-existing style
issues.
Signed-off-by: Maarten Lankhorst
On 23/02/2023 01:42, Laurent Pinchart wrote:
The DORCR register controls the routing of clocks and data between DU
channels within a group. For groups that contain a single channel,
there's no routing option to control, and some fields of the register
are then reserved. On Gen2 those reserved fie
The current DP driver directly enables or disables the necessary control
resources based on code flow. This could disable a required resource that
is needed in a different usecase. It can also lead to excessive voting of
a resource and may increase power consumption.
The pm_runtime framework can s
The eDP panel is identified and enumerated during probe of the panel-edp
driver. The current DP driver triggers this panel-edp driver probe while
getting the panel-bridge associated with the eDP panel from the platform
driver bind. If the panel-edp probe is deferred, then the whole bunch of
MDSS pa
The DP driver resources are currently enabled and disabled directly based on
code flow.
As mentioned in bug 230631602, we want to do the following:
1) Refactor the dp/edp parsing code to move it to probe (it is currently done
in bind).
2) Then bind all the power resources needed for AUX in pm_r
On 23/02/2023 01:42, Laurent Pinchart wrote:
The DORCR fields were documented in the R-Car H1 datasheet with 1-based
named, and then got renamed to 0-based in Gen2. The 0-based names are
used for Gen3 and Gen4, making H1 an outlier. Rename the field macros to
make them 0-based, in order to increa
Wrong subject line? Should be drm/gma500?
Alex
On Mon, Feb 20, 2023 at 10:45 PM Jiapeng Chong
wrote:
>
> No functional modification involved.
>
> drivers/gpu/drm/gma500/cdv_device.c:218 cdv_errata() warn: inconsistent
> indenting.
>
> Reported-by: Abaci Robot
> Link: https://bugzilla.openanol
On 23.02.2023 14:06, Dmitry Baryshkov wrote:
> On Thu, 23 Feb 2023 at 14:07, Konrad Dybcio wrote:
>>
>> According to the vendor sources, it's equal to 16, which makes hbb_lo
>> equal to 3.
>
> I think we might be stricken with the ddr kind difference here, but I
> would not bet on it.
It total
(Resend this with plaintext mode. Sorry for the previous spam.)
Hi Rob,
After some internal discussions, we decided to drop this series
because the driver is trying to do runtime routing of the display
signals, which is not supported by the current DRM system, even if we
can describe the design i
Since new platform data was required in Panfrost for getting GPU DVFS
finally working on MediaTek SoCs, add a new "mediatek,mt8183b-mali"
compatible.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Rob Herring
---
.../bindings/gpu/arm,mali-bifrost.yaml| 19 +++
1
From: Alyssa Rosenzweig
Required for Mali-G57 on the Mediatek MT8192 and MT8195, which
uses even more power domains than the MT8183 before it.
Signed-off-by: Alyssa Rosenzweig
[Angelo: Removed unneeded "sram" supply, added mt8195 to commit description]
Co-developed-by: AngeloGioacchino Del Regn
MediaTek MT8186 has a Mali-G52 MC2 2EE (Bifrost): add a new compatible
and platform data using the same supplies list as "mt8183_b" (only one
regulator), and a new pm_domains list with only two power domains.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/panfrost/panfrost_drv.c
From: Alyssa Rosenzweig
MediaTek MT8192 has a Mali-G57 with a special GPU ID. Add its GPU ID,
but treat it as otherwise identical to a standard Mali-G57.
We do _not_ fix up the GPU ID here -- userspace needs to be aware of the
special GPU ID, in case we find functional differences between
MediaT
The "mediatek,mt8183-mali" compatible uses platform data that calls for
getting (and managing) two regulators ("mali" and "sram") but devfreq
does not support this usecase, resulting in DVFS not working.
Since a lot of MediaTek SoCs need to set the voltages for the GPU SRAM
regulator in a specific
MT8186 has a Mali-G52 MC2 2EE GPU (two cores): add a binding with
two power domains (one per core) for it.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/gpu/arm,mali-bifrost.yaml | 18 ++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetre
From: Alyssa Rosenzweig
Increase the MAX_PM_DOMAINS constant from 3 to 5, to support the
extra power domains required by the Mali-G57 on the MT8192.
Signed-off-by: Alyssa Rosenzweig
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_dev
The MediaTek MT8195 SoC has a Mali G57 MC5 (Valhall-JM) and has the
same number of power domains and requirements as MT8192 in terms of
bindings.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 5 +
1 file
In preparation for adding new bindings for new MediaTek SoCs, split out
the power-domain-names and power-domainsvariation from the `else` in
the current mediatek,mt8183-mali conditional.
The sram-supply part is left in place to be disallowed for anything
that is not compatible with "mediatek,mt818
From: Chen-Yu Tsai
In commit a7a596cd3115 ("dt-bindings: gpu: mali-bifrost: Add Mediatek
MT8183"), "power-domain-names" was added to the mt8183-mali sub-schema,
but was not added to the base mali-bifrost schema. Because validation
happens for the base schema and any sub-schemas separately, this c
Changes in v3:
- Changed MT8186 bindings to declare only two power domains
- Added a commit introducing MT8186 specific platform data to
panfrost_drv
Changes in v2:
- Add power-domain-names commit from Chen-Yu to the series
- Kept sram-supply in base schema, overridden for non-MediaTek
- A
MediaTek MT8192 (and similar) needs five power domains for the
Mali GPU and no sram-supply: change the binding to allow so.
Fixes: 5d82e74a97c2 ("dt-bindings: Add compatible for Mali Valhall (JM)")
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Rob Herring
---
.../bindings/gpu/arm,mali
Hi Rob,
After some internal discussions, we decided to drop this series because the
driver is trying to do runtime routing of the display signals, which is not
supported by the current DRM system, even if we can describe the design in
the device tree. I'm explaining our use case as a record, and I
Il 23/02/23 03:43, Chen-Yu Tsai ha scritto:
On Wed, Feb 22, 2023 at 5:13 PM AngeloGioacchino Del Regno
wrote:
Il 22/02/23 09:37, Chen-Yu Tsai ha scritto:
On Tue, Feb 21, 2023 at 11:37 PM AngeloGioacchino Del Regno
wrote:
Get GPU support on MT8186 by adding its compatible.
Signed-off-by: A
Hi,
On 22/02/2023 17:28, Nicolas Dufresne wrote:
Hi Tomi,
Le mercredi 21 décembre 2022 à 11:24 +0200, Tomi Valkeinen a écrit :
Add Y210, Y212 and Y216 formats.
Signed-off-by: Tomi Valkeinen
---
.../media/v4l/pixfmt-packed-yuv.rst | 49 ++-
drivers/media/v4l2-core
On Thu, 23 Feb 2023 at 14:07, Konrad Dybcio wrote:
>
> According to the vendor sources, it's equal to 16, which makes hbb_lo
> equal to 3.
I think we might be stricken with the ddr kind difference here, but I
would not bet on it.
>
> Fixes: 840d10b64dad ("drm: msm: Add 680 gpu to the adreno gpu
On Thu, 2023-02-23 at 15:04 +0800, Meng Tang wrote:
> A privilege escalation vulnerability was found in vmwgfx driver
> in drivers/gpu/drm/vmwgfx/vmwgfx_drv.c in GPU component of Linux
> kernel with device file '/dev/dri/renderD128 (or Dxxx)'. This flaw
> allows a local attacker with a user account
Ping.
Best Regards,
- Maíra Canal
On 2/2/23 08:19, Maíra Canal wrote:
Currently, the array of BOs that are lookup up at the start of exec is being
instantiated as drm_gem_dma_object, which is not needed and makes it difficult
to use the drm_gem_objects_lookup() helper. Therefore, replace
drm_ge
Am 23.02.23 um 13:19 schrieb Maíra Canal:
The missing parentheses prevents the function to be rendered as a link
in the documentation. So, add the missing parentheses to the function on
the documentation.
Signed-off-by: Maíra Canal
Good catch, Reviewed-by: Christian König
Going to push this
The missing parentheses prevents the function to be rendered as a link
in the documentation. So, add the missing parentheses to the function on
the documentation.
Signed-off-by: Maíra Canal
---
drivers/dma-buf/dma-buf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/
Fix some names around struct fb_ops to better fit the overall naming
conventions. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/gma500/fbdev.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/gma500/fbdev.c b/dri
Remove fbdev emulations' open and close implementaitons for the VM. The
functions are empty. Also update the naming of the VMA code.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/gma500/fbdev.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/g
Implement fbdevemulation on top of struct drm_client and its helpers.
This ad-hoc interfaces for restoring and closing fbdev emulation with
per-client callback for hotplugging, restoring and unregistering.
A single function, psb_fbdev_setup(), starts fbdev emulation after
the DRM device has been r
Inline psbfb_create() into its only caller psbfb_probe(). Streamline
the color-depth selection.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/gma500/fbdev.c | 65 ++
1 file changed, 26 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/gma500/fbde
Instead of the DRM framebuffer, pass the FB info strcuture to the
fbdev page-fault handler psb_fbdev_vm_fault(). The framebuffer is a
high-level data structure and does not belong into fault handling.
The fb_info has all necessary information. Also set fix.smem_start
to the correct value (the begin
Move the fbdev emulation from framebuffer.c into fbdev.c. Only build
the source code if the Kconfig symbol has been selected. Remaining in
framebuffer.c is gma500's code for DRM frambuffers. No functional
hanges.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/gma500/Makefile | 1 +
Remove unnecessary include statements from framebuffer.c. No
functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/gma500/framebuffer.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/drivers/gpu/drm/gma500/framebuffer.c
b/drivers/gpu/drm/gma500/framebuffe
Convert gma500's fbdev code to drm_client. Replace to the current
ad-hoc integration. The conversion includes a number of cleanups.
Only build fbdev support if the config option has been set.
Tested on Cedarview HW.
Thomas Zimmermann (7):
drm/gma500: Remove unnecessary include statements
drm/
Am 23.02.23 um 07:27 schrieb Hogander, Jouni:
On Wed, 2023-02-22 at 15:13 -0500, Rodrigo Vivi wrote:
On Wed, Feb 22, 2023 at 03:17:55PM +0100, Werner Sembach wrote:
On these Barebones PSR 2 is recognized as supported but is very
buggy:
- Upper third of screen does sometimes not updated, resul
On 23.02.2023 13:06, Konrad Dybcio wrote:
> GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be
> specified under the GPU node, just like their older cousins.
> Account for that.
>
> Signed-off-by: Konrad Dybcio
> ---
[...]
> -then: # Since Adreno 6xx series clocks should b
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