Hi
Am 05.09.25 um 04:43 schrieb Zizhi Wo:
[BUG]
Recently, we encountered a KASAN warning as follows:
kasan_report+0xaf/0xe0 mm/kasan/report.c:588
fb_pad_aligned_buffer+0x12f/0x150 drivers/video/fbdev/core/fbmem.c:116
ccw_putcs_aligned drivers/video/fbdev/core/fbcon_ccw.c:119 [inline]
ccw_putcs+
пн, 22 вер. 2025 р. о 09:23 Mikko Perttunen пише:
>
> On Monday, September 22, 2025 2:13 PM Svyatoslav Ryhel wrote:
> > пн, 22 вер. 2025 р. о 07:44 Mikko Perttunen пише:
> > >
> > > On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> > > > Simplify format align calculations by sligh
Am 12.09.25 um 19:00 schrieb Samasth Norway Ananda:
Fix integer overflow vulnerabilities in fbcon_do_set_font() where font
size calculations could overflow when handling user-controlled font
parameters.
The vulnerabilities occur when:
1. CALC_FONTSZ(h, pitch, charcount) performs h * pith * ch
On Monday, September 22, 2025 1:58 PM Svyatoslav Ryhel wrote:
> пн, 22 вер. 2025 р. о 07:54 Mikko Perttunen пише:
> >
> > On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> > > Increase maximum VI clock frequency to 450MHz to allow correct work with
> > > high resolution camera sens
пн, 22 вер. 2025 р. о 08:16 Mikko Perttunen пише:
>
> On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> > Add support for MIPI CSI device and calibration logic found in Tegra20 and
> > Tegra30 SoC.
>
> The patch is on the longer side. I'd add some more explanation in the commit
>
On Monday, September 22, 2025 2:19 PM Svyatoslav Ryhel wrote:
> пн, 22 вер. 2025 р. о 08:16 Mikko Perttunen пише:
> >
> > On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> > > Add support for MIPI CSI device and calibration logic found in Tegra20 and
> > > Tegra30 SoC.
> >
> > The
пн, 22 вер. 2025 р. о 08:16 Mikko Perttunen пише:
>
> On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> > Add support for MIPI CSI device and calibration logic found in Tegra20 and
> > Tegra30 SoC.
>
> The patch is on the longer side. I'd add some more explanation in the commit
>
пн, 22 вер. 2025 р. о 07:44 Mikko Perttunen пише:
>
> On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> > Simplify format align calculations by slightly modifying supported formats
> > structure.
> >
> > Signed-off-by: Svyatoslav Ryhel
> > ---
> > drivers/staging/media/tegra-vide
On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> Add support for Bayer formats (RAW8 and RAW10) and YUV422_8 1X16 versions
> of existing YUV422_8 2X8.
>
> Signed-off-by: Svyatoslav Ryhel
> ---
> drivers/staging/media/tegra-video/tegra20.c | 72 -
> 1 file cha
пн, 22 вер. 2025 р. о 07:54 Mikko Perttunen пише:
>
> On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> > Increase maximum VI clock frequency to 450MHz to allow correct work with
> > high resolution camera sensors.
> >
> > Signed-off-by: Svyatoslav Ryhel
> > ---
> > drivers/stagi
On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> Simplify format align calculations by slightly modifying supported formats
> structure.
>
> Signed-off-by: Svyatoslav Ryhel
> ---
> drivers/staging/media/tegra-video/tegra20.c | 41 -
> 1 file changed, 16 inser
On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> VI in Tegra20/Tegra30 has 2 VI outputs with different set of supported
> formats. Convert output registers to macros for simpler work with both
> outputs since apart formats their layout matches.
>
> Signed-off-by: Svyatoslav Ryhel
On 09/19/2025, Frank Li wrote:
> On Fri, Jul 04, 2025 at 05:03:52PM +0800, Liu Ying wrote:
>> CRTC(s) could still be running after the DRM device is unplugged by
>> calling drm_dev_unplug(), because the CRTC disablement logic is
>> protected and bypassed by the drm_dev_enter()/drm_dev_exit() pair.
Hello,
syzbot found the following issue on:
HEAD commit:b320789d6883 Linux 6.17-rc4
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=16ceae6258
kernel config: https://syzkaller.appspot.com/x/.config?x=d4703ac89d9e185a
dashboard link: https://syzkaller.ap
On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> The avdd-dsi-csi-supply is CSI power supply not VI, hence move it to
> proper place.
>
> Signed-off-by: Svyatoslav Ryhel
> ---
> drivers/staging/media/tegra-video/csi.c | 19 ++-
> drivers/staging/media/tegra-video
On 09/19/2025, Frank Li wrote:
> On Fri, Jul 04, 2025 at 05:03:54PM +0800, Liu Ying wrote:
>> Display Prefetch Resolve Channel(DPRC) is a part of a prefetch engine.
>> It fetches display data, transforms it to linear format and stores it
>> to DPRC's RTRAM. PRG, as the other part of a prefetch eng
From: Baihan Li
There are some bugfix for hibmc-drm driver.
---
ChangeLog:
v5 -> v6:
- use HPD status in DP detect_ctx(), suggested by Dmitry Baryshkov.
v4 -> v5:
- Because some of patches are applied, this series only contains the rest of
them.
- fix the commit and DP detect_ctx(), sugges
On 09/19/2025, Frank Li wrote:
> On Fri, Jul 04, 2025 at 05:04:01PM +0800, Liu Ying wrote:
>> One prefetch engine consists of one DPR channel and one or two PRGs.
>> Each PRG handles one planar in a pixel format. Every FetchUnit used
>> by KMS may attach to a PRG and hence use a prefetch engine.
On 09/19/2025, Frank Li wrote:
> On Fri, Jul 04, 2025 at 05:03:55PM +0800, Liu Ying wrote:
>> In TCON operation mode, sync signals from FrameGen are ignored, but
>> a much more customized output timing can be generated by the TCON
>> module. By using TCON operaton mode, generate KACHUNK signal alo
On 09/10/2025, Shengjiu Wang wrote:
> Hi
>
> On Tue, Sep 9, 2025 at 2:39 PM Maxime Ripard wrote:
>>
>> Hi,
>>
>> On Wed, Sep 03, 2025 at 06:41:05PM +0800, Shengjiu Wang wrote:
>>> On Tue, Sep 2, 2025 at 12:52 AM Luca Ceresoli
>>> wrote:
Hello Shengjiu,
On Thu, 21 Aug 2025 15
From: Baihan Li
When using command rmmod and insmod, there is no showing in second time
insmoding. Because DP controller won't send HPD signals, if connection
doesn't change or controller isn't reset. So add reset before unreset
in hibmc_dp_hw_init().
And also need to move the HDCP cfg after DP
From: Baihan Li
Add colorbar disable operation before reset chontroller, to make sure
colorbar status is clear in the DP init, so if rmmod the driver and the
previous colorbar configuration will not affect the next time insmod the
driver.
Fixes: 3c7623fb5bb6 ("drm/hisilicon/hibmc: Enable this ho
From: Baihan Li
If DP is connected, check the DP BW in mode_valid_ctx() to ensure
that DP's link rate supports high-resolution data transmission.
Fixes: 0ab6ea261c1f ("drm/hisilicon/hibmc: add dp module in hibmc")
Signed-off-by: Baihan Li
Signed-off-by: Yongbang Shi
Reviewed-by: Dmitry Baryshk
From: Baihan Li
The issue is that drm_connector_helper_detect_from_ddc() returns wrong
status when plugging or unplugging the monitor. Use HPD pin status in
DP's detect_ctx() for real physcal monitor in/out, and keep using
detect_frome_ddc() if it's the first time to call detect because of
insmod
From: Chaoyi Chen
This series focuses on adding Type-C DP support for USBDP PHY and DP
driver. The USBDP PHY and DP will perceive the changes in cable status
based on the USB PD and Type-C state machines provided by TCPM. Before
this, the USBDP PHY and DP controller of RK3399 sensed cable state
c
From: Chaoyi Chen
Let's make the ports nodes of cdn_dp in the same style as the other
display interface, and match the style of ports's yaml.
Signed-off-by: Chaoyi Chen
---
Changes in v4:
- Remove unnecessary #address/#size-cells
(no changes since v1)
arch/arm64/boot/dts/rockchip/rk3399-bas
From: Chaoyi Chen
The RK3399 has two USB/DP combo PHY and one CDN-DP controller. And
the CDN-DP can be switched to output to one of the PHYs. If both ports
are plugged into DP, DP will select the first port for output.
This patch adds support for multiple bridges, enabling users to flexibly
sele
From: Chaoyi Chen
This patch add support for get PHY lane info without help of extcon.
There is no extcon needed if the Type-C controller is present. In this
case, the lane info can be get from PHY instead of extcon.
The extcon device should still be supported if Type-C controller is
not presen
From: Chaoyi Chen
The RK3399 SoC integrates two USB/DP combo PHYs, each of which
supports software-configurable pin mapping and DisplayPort lane
assignment. These capabilities enable the PHY itself to handle both
mode switching and orientation switching, based on the Type-C plug
orientation and U
From: Chaoyi Chen
Add default DRM AUX HPD bridge device when register DisplayPort
altmode. That makes it redundant for each Type-C driver to implement
a similar registration process in embedded scenarios.
Signed-off-by: Chaoyi Chen
---
drivers/usb/typec/altmodes/displayport.c | 27
From: Chaoyi Chen
The RK3399 EVB IND board has a Type-C interface DisplayPort.
It use fusb302 chip as Type-C controller.
fusb302 chip ---> USB/DP PHY0 <> CDN-DP controller
Signed-off-by: Chaoyi Chen
---
(no changes since v4)
Changes in v3:
- Fix wrong vdo value.
- Fix port node in usb-c-
From: Rajeev Tapadia
The mipi_dsi_dcs_write_buffer_chatty() helper is redundant and
non-intuitive. It has been removed in favour of
mipi_dsi_dcs_write_buffer_multi(), which handles multiple DSI writes with
proper error accumulation.
Signed-off-by: Rajeev Tapadia
---
drivers/gpu/drm/drm_mipi_ds
Quoting Svyatoslav Ryhel (2025-09-06 06:16:52)
> Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.
>
> Signed-off-by: Svyatoslav Ryhel
> ---
Acked-by: Stephen Boyd
Quoting Nicolas Frattaroli (2025-06-23 09:05:47)
> The sp7021 clock driver has its own shifted high word mask macro,
> similar to the ones many Rockchip drivers have.
>
> Remove it, and replace instances of it with hw_bitfield.h's
> FIELD_PREP_WM16 macro, which does the same thing except in a comm
On Fri, Sep 19, 2025 at 10:17:00AM +, Eliav Farber wrote:
> This series includes a total of 27 patches, to align minmax.h of
> v5.15.y with v6.17-rc6.
>
> The set consists of 24 commits that directly update minmax.h:
> 1) 92d23c6e9415 ("overflow, tracing: Define the is_signed_type() macro
>
VeriSilicon is a Silicon IP vendor, which is the current owner of
Vivante series video-related IPs and Hantro series video codec IPs.
Add a vendor prefix for this company.
Signed-off-by: Icenowy Zheng
---
No changes in v2.
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file c
Quoting Maíra Canal (2025-07-31 14:06:19)
> Although minimizing the clock rate is the best for most scenarios, as
> stated in commit 4d85abb0fb8e ("clk: bcm: rpi: Enable minimize for all
> firmware clocks"), when it comes to the GPU, it's ideal to have the
> maximum rate allowed.
>
> Add an option
Quoting Maíra Canal (2025-07-31 14:06:18)
> Currently, when we prepare or unprepare RPi's clocks, we don't actually
> enable/disable the firmware clock. This means that
> `clk_disable_unprepare()` doesn't actually change the clock state at
> all, nor does it lowers the clock rate.
>
> From the Mai
Quoting Maíra Canal (2025-07-31 14:06:17)
> From: Stefan Wahren
>
> In contrary to raspberrypi_fw_set_rate(), the ops for is_prepared() and
> recalc_rate() silently ignore firmware errors by just returning 0.
> Since these operations should never fail, add at least error logs
> to inform the user
Quoting Janne Grunau (2025-08-28 07:01:44)
> After discussion with the devicetree maintainers we agreed to not extend
> lists with the generic compatible "apple,nco" anymore [1]. Use
> "apple,t8103-nco" as base compatible as it is the SoC the driver and
> bindings were written for.
>
> [1]:
> htt
Quoting Janne Grunau (2025-08-28 07:01:45)
> After discussion with the devicetree maintainers we agreed to not extend
> lists with the generic compatible "apple,nco" anymore [1]. Use
> "apple,t8103-nco" as base compatible as it is the SoC the driver and
> bindings were written for.
>
> The block f
remove a space before an open square bracket,
fixes a linter error
Signed-off-by: Shreyas Muppana
---
drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
ind
imx6sx.dtsi has the following lcdif entries:
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
This causes the following dt-schema warning:
['fsl,imx6sx-lcdif', 'fsl,imx28-lcdif'] is too long
To keep DT compatibility, document 'fsl,imx28-lcdif' as a possible
'fsl,imx6sx-lcdif' fallback.
Sign
Add routines to support allocation of large order zone device folios
and helper functions for zone device folios, to check if a folio is
device private and helpers for setting zone device data.
When large folios are used, the existing page_free() callback in
pgmap is called when the folio is freed
The mediatek atomic_check implementation uses the deprecated
drm_atomic_get_existing_crtc_state() helper.
This hook is called as part of the global atomic_check, thus before the
states are swapped. The existing state thus points to the new state, and
we can use drm_atomic_get_new_crtc_state() inst
On Sun Sep 21, 2025 at 11:36 AM CEST, Greg KH wrote:
> Your example code using this is nice, and it shows how to set up, and
> query these bits, but that's not anything anyone actually does in the
> kernel, what they want to do is read/write from hardware with this.
>
> So, how does that work? Whe
On Sun Sep 21, 2025 at 2:45 PM CEST, Greg KH wrote:
> Again, regmap handles this all just fine, why not just make bindings to
> that api here instead?
The idea is to use this for the register!() macro, e.g.
register!(NV_PMC_BOOT_0 @ 0x, "Basic revision information about
the GPU"
Verisilicon has a series of display controllers prefixed with DC and
with self-identification facility like their GC series GPUs.
Add a device tree binding for it.
Depends on the specific DC model, it can have either one or two display
outputs, and each display output could be set to DPI signal o
On Sun, Sep 21, 2025 at 02:33:56PM +0200, Benno Lossin wrote:
> On Sun Sep 21, 2025 at 11:36 AM CEST, Greg KH wrote:
> > On Sat, Sep 20, 2025 at 02:22:27PM -0400, Joel Fernandes wrote:
> >> The bitfield-specific into new macro. This will be used to define
> >> structs with bitfields, similar to C l
On Sun Sep 21, 2025 at 11:36 AM CEST, Greg KH wrote:
> On Sat, Sep 20, 2025 at 02:22:27PM -0400, Joel Fernandes wrote:
>> The bitfield-specific into new macro. This will be used to define
>> structs with bitfields, similar to C language.
>>
>> Reviewed-by: Elle Rhumsaa
>> Signed-off-by: Joel Fern
On Sat, Sep 20, 2025 at 2:39 AM Joel Fernandes wrote:
>
> The C checks use BUILD_BUG_ON, in rust-for-linux we have build_assert but it
> is fragile and depends on the value being a constant.
What do you mean?
`build_assert!` works essentially like `BUILD_BUG_ON`, i.e. after the
optimizer, and do
On Sun, Sep 21, 2025 at 11:59:05AM +0200, Miguel Ojeda wrote:
> On Sun, Sep 21, 2025 at 11:36 AM Greg KH wrote:
> >
> > And where does this allow us to define things like BIT(2) for values?
> > (ok, that's kind of not the point of this patch series, but it will come
> > up over time...)
>
> We ha
On Sun, Sep 21, 2025 at 11:36 AM Greg KH wrote:
>
> And where does this allow us to define things like BIT(2) for values?
> (ok, that's kind of not the point of this patch series, but it will come
> up over time...)
We have the `bits` module since 6.17:
https://rust.docs.kernel.org/kernel/bi
T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller (paired
with DesignWare HDMI TX PHY Gen2) that takes the "DP" output from the
display controller.
Add a driver for this controller utilizing the common DesignWare HDMI
code in the kernel.
Signed-off-by: Icenowy Zheng
---
Changes in
On Sat, Sep 20, 2025 at 02:22:27PM -0400, Joel Fernandes wrote:
> The bitfield-specific into new macro. This will be used to define
> structs with bitfields, similar to C language.
>
> Reviewed-by: Elle Rhumsaa
> Signed-off-by: Joel Fernandes
> ---
> drivers/gpu/nova-core/bitfield.rs| 314 +
T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller paired
with DesignWare HDMI PHY, with an extra clock gate for HDMI pixel clock
and two reset controls.
Add a device tree binding to it.
Signed-off-by: Icenowy Zheng
Reviewed-by: Krzysztof Kozlowski
---
Changes in v2:
- Re-aligned
T-Head TH1520 SoC contains a Verisilicon DC8200 display controller
(called DPU in manual) and a Synopsys DesignWare HDMI TX controller.
Add device tree nodes to them.
Signed-off-by: Icenowy Zheng
---
No changes in v2.
arch/riscv/boot/dts/thead/th1520.dtsi | 70 +++
1 fi
This patchset tries to add a driver for Verisilicon DC8200 driver, and
demonstrates the driver on T-Head TH1520 with its HDMI output.
This display controller IP is used on StarFive JH7110 too, but as the
HDMI controller used there isn't as common as the DesignWare one, I
choose to use TH1520 in th
Lichee Pi 4A board features a HDMI Type-A connector connected to the
HDMI TX controller of TH1520 SoC.
Add a device tree node describing the connector, connect it to the HDMI
controller, and enable everything on this display pipeline.
Signed-off-by: Icenowy Zheng
---
No changes in v2.
.../boot
As I am the author of this rewritten driver, it makes sense for me to be
the maintainer.
Confirm this in MAINTAINERS file.
Signed-off-by: Icenowy Zheng
---
No changes in v2.
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 98af9dd3664f5..34
This is a from-scratch driver targeting Verisilicon DC-series display
controllers, which feature self-identification functionality like their
GC-series GPUs.
Only DC8200 is being supported now, and only the main framebuffer is set
up (as the DRM primary plane). Support for more DC models and more
Before the MIPI DSI clock source can be configured, the target divide
ratio needs to be known.
Signed-off-by: Chris Brandt
---
v1->v2:
- Add spaces around '/' in comments
- Add target argument in new API
---
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 18 ++
1 file changed,
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