MIGRATE_VMA_SELECT_COMPOUND will be used to select THP pages during
migrate_vma_setup() and MIGRATE_PFN_COMPOUND will make migrating device
pages as compound pages during device pfn migration.
migrate_device code paths go through the collect, setup and finalize
phases of migration.
The entries in
Change page_free to folio_free to make the folio support for
zone device-private more consistent. The PCI P2PDMA callback
has also been updated and changed to folio_free() as a result.
For drivers that do not support folios (yet), the folio is
converted back into page via &folio->page and the page
This patch series introduces support for Transparent Huge Page
(THP) migration in zone device-private memory. The implementation enables
efficient migration of large folios between system memory and
device-private memory
Background
Current zone device-private memory implementation only supports P
Hi
Am 23.09.25 um 11:33 schrieb Maxime Ripard:
On Mon, Sep 15, 2025 at 03:12:11PM +0200, Thomas Zimmermann wrote:
Hi
Am 15.09.25 um 13:27 schrieb Maxime Ripard:
On Tue, Sep 02, 2025 at 03:18:17PM +0200, Thomas Zimmermann wrote:
Hi
Am 02.09.25 um 10:32 schrieb Maxime Ripard:
Bridges impleme
Add HAS_CASF macro to check whether platform supports
the content adaptive sharpness capability or not.
v2: Update commit message[Ankit]
v3: Remove \n from middle[Jani]
v4: Remove the logging part
Signed-off-by: Nemesa Garg
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dis
Add common structure to drm_connector and a set of high-level helpers to
be used by DRM drivers to implement DisplayPort support.
Note: this is currently early WIP patch, sent in order to kick off the
discussion and the hackaton at the XDC 2025.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/d
On Tue, Sep 30, 2025 at 09:12:21PM +0200, Helge Deller wrote:
> On 9/15/25 08:36, Janne Grunau wrote:
> > The pm_domain cleanup can not be devres managed as it uses struct
> > simplefb_par which is allocated within struct fb_info by
> > framebuffer_alloc(). This allocation is explicitly freed by
>
On 9/26/2025 5:07 PM, Nemesa Garg wrote:
Add the register bits related to filter lut values.
These values are golden values and these value has
to be loaded one time while enabling the casf.
v2: update commit message[Ankit]
v3: Make filter_load fn name same[Jani]
v4: Define the filter macros h
On 2025-10-01 at 12:02 +1000, John Hubbard wrote...
> On 9/30/25 6:16 AM, Alistair Popple wrote:
> > Changes since v2:
> >
> > The main change since v2 has been to make all firmware bindings
> > completely opaque. It has been made clear this is a pre-requisite for
>
> Any hints about where to se
ср, 1 жовт. 2025 р. о 07:38 Mikko Perttunen пише:
>
> On Friday, September 26, 2025 12:16 AM Svyatoslav Ryhel wrote:
> > Simplify format align calculations by slightly modifying supported formats
> > structure. Adjusted U and V offset calculations for planar formats since
> > YUV420P bits per pixe
On 9/24/25 22:47, dongwon@intel.com wrote:
> From: Dongwon Kim
>
> This patch series introduces support for handling hibernation (S4)
> in the virtio-gpu driver by implementing .freeze and .restore hooks,
> along with a PM notifier to restore GPU resources upon resume.
>
> Patch 1 adds virtg
On 9/27/25 09:50, Albin Babu Varghese wrote:
KASAN reports vmalloc-out-of-bounds writes in sys_imageblit during console
resize operations. The crash happens when bit_putcs renders characters
outside the allocated framebuffer region.
Call trace: vc_do_resize -> clear_selection -> invert_screen ->
The as_in_use_mask device state variable is no longer in use.
Reviewed-by: Boris Brezillon
Signed-off-by: Adrián Larumbe
---
drivers/gpu/drm/panfrost/panfrost_device.h | 1 -
drivers/gpu/drm/panfrost/panfrost_mmu.c| 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/panfrost
On 2025-09-30 at 23:26 +1000, Danilo Krummrich wrote...
> On 9/30/25 3:16 PM, Alistair Popple wrote:
> > Changes since v2:
> >
> > The main change since v2 has been to make all firmware bindings
> > completely opaque. It has been made clear this is a pre-requisite for
> > this series to progress
On Tue, Sep 30, 2025 at 11:57:07PM +, Wei Liu wrote:
> On Fri, Sep 05, 2025 at 06:09:50PM -0700, Mukesh Rathor wrote:
> > At present, drivers/Makefile will subst =m to =y for CONFIG_HYPERV
> > for hv subdir. Also, drivers/hv/Makefile replaces =m to =y to build in
> > hv_common.c that is needed
On 2025-09-29 at 22:49 +1000, Danilo Krummrich wrote...
> On Mon Sep 29, 2025 at 9:39 AM CEST, Alistair Popple wrote:
> > On 2025-09-29 at 17:06 +1000, Danilo Krummrich wrote...
> >> On Mon Sep 29, 2025 at 2:19 AM CEST, Alistair Popple wrote:
> >> > On 2025-09-26 at 22:00 +1000, Danilo Krummrich
On Fri, Sep 05, 2025 at 06:09:50PM -0700, Mukesh Rathor wrote:
> At present, drivers/Makefile will subst =m to =y for CONFIG_HYPERV
> for hv subdir. Also, drivers/hv/Makefile replaces =m to =y to build in
> hv_common.c that is needed for the drivers. Moreover, vmbus driver is
> built if CONFIG_HYPE
6.12-stable review patch. If anyone has any objections, please let me know.
--
From: Nirmoy Das
commit c7c31f8dc54aa3c9b2c994b5f1ff7e740a654e97 upstream.
The busy-waiting in `mdelay()` can cause CPU stalls and kernel timeouts
during boot.
Signed-off-by: Nirmoy Das
Reviewed-b
On 2025-09-30 at 21:58 +1000, Miguel Ojeda
wrote...
> On Tue, Sep 30, 2025 at 1:42 PM Alistair Popple wrote:
> >
> > Thanks. Is it still expected that `#[allow(clippy::incompatible_msrv)]` is
> > required? Just adding it to `rust_allowed_features` doesn't make the
> > warning go
> > away withou
On 8/30/25 14:47, Qianfeng Rong wrote:
Change the 'ret' variable in of_platform_mb862xx_probe() from unsigned long
to int, as it needs to store either negative error codes or zero.
Storing the negative error codes in unsigned type, doesn't cause an issue
at runtime but can be confusing. Addition
On Wed, 1 Oct 2025 at 07:59, Krzysztof Kozlowski wrote:
>
> On Wed, 1 Oct 2025 at 00:46, Marek Szyprowski
> wrote:
> >
> > Hi Krzysztof,
> >
> > On 30.09.2025 07:54, Krzysztof Kozlowski wrote:
> > > On Tue, 30 Sept 2025 at 12:56, Himanshu Dewangan
> > > wrote:
> > >> From: Nagaraju Siddineni
On Tue, Sep 30, 2025 at 05:42:51PM +0800, Damon Ding wrote:
> In order to unify the handling of the panel and bridge, apply
> panel_bridge helpers for Analogix DP driver. With this patch, the
> bridge support will also become available.
>
> The following changes have ben made:
> - Apply plane_brid
On 9/18/25 06:01, Michael Kelley wrote:
From: Prasanna Kumar T S M Sent: Wednesday,
September 17, 2025 7:03 AM
The Hyper-V DRM driver is available since kernel version 5.14 and it
provides full KMS support and fbdev emulation via the DRM fbdev helpers.
Deprecate this driver in favor of Hyper-
Add helpers to query the DP DSC sink device's per-slice throughput as
well as a DSC branch device's overall throughput and line-width
capabilities.
v2 (Ville):
- Rename pixel_clock to peak_pixel_rate, document what the value means
in case of MST tiled displays.
- Fix name of drm_dp_dsc_branch_ma
Pass the DPCD sink/branch device descriptor along with the
is_branch/sink flag to intel_dp_get_dsc_sink_cap(). These will be used
by a follow up change to read out the branch device's DSC overall
throughput/line width capabilities and to detect a throughput/link-bpp
quirk.
Reported-and-tested-by:
On Tue, Sep 30, 2025 at 10:52:47AM -0600, Alex Williamson wrote:
> On Tue, 30 Sep 2025 11:34:08 -0300
> Jason Gunthorpe wrote:
>
> > On Tue, Sep 30, 2025 at 12:50:47PM +, Shameer Kolothum wrote:
> >
> > > This is where hisi_acc reports a different BAR size as it tries to hide
> > > the migra
On Tue, Sep 30, 2025 at 10:45:36AM -0400, Joel Fernandes wrote:
> Similar to bitmap.rs, add hardening to print errors or assert if the
> setter API is used to write out-of-bound values.
>
> Suggested-by: Yury Norov
> Signed-off-by: Joel Fernandes
> ---
> rust/kernel/bitfield.rs| 32
On Tue, 2025-09-30 at 23:16 +1000, Alistair Popple wrote:
> + let (mbox0, mbox1) = gsp_falcon.boot(
> + bar,
> + Some(libos_handle as u32),
> + Some((libos_handle >> 32) as u32),
> + )?;
The only time .boot() is called with None for mbox1 is with fwse
Similar to bitmap.rs, add hardening to print errors or assert if the
setter API is used to write out-of-bound values.
Suggested-by: Yury Norov
Signed-off-by: Joel Fernandes
---
rust/kernel/bitfield.rs| 32 +++-
security/Kconfig.hardening | 9 +
2 files c
In order to prevent the user from directly accessing/wrapping the inner
value of the struct, provide a new storage type to wrap the inner value.
The bitfield framework can then control access better. For instance, we
can zero out undefined bits to prevent undefined behavior of bits that
are not def
On 30/09/2025 12:30, Boris Brezillon wrote:
On Mon, 29 Sep 2025 22:03:10 +0200
Loïc Molinari wrote:
+unsigned long drm_gem_get_unmapped_area(struct file *filp, unsigned long uaddr,
+ unsigned long len, unsigned long pgoff,
+
On Tue, 30 Sep 2025 10:57:48 +0300
Leon Romanovsky wrote:
> On Mon, Sep 29, 2025 at 03:17:40PM -0600, Alex Williamson wrote:
> > On Sun, 28 Sep 2025 17:50:17 +0300
> > Leon Romanovsky wrote:
> >
> > > From: Leon Romanovsky
> > >
> > > Add new kernel config which indicates support for dma-bu
On Tue Sep 30, 2025 at 4:45 PM CEST, Joel Fernandes wrote:
> MAINTAINERS | 7 +
> drivers/gpu/nova-core/falcon.rs | 2 +-
> drivers/gpu/nova-core/falcon/gsp.rs | 4 +-
> drivers/gpu/nova-core/falcon/sec2.rs | 2 +-
> driver
Hi
Am 16.09.25 um 17:00 schrieb Michael Kelley:
From: Thomas Zimmermann Sent: Tuesday, September 16, 2025
1:31 AM
Hi
Am 09.09.25 um 05:29 schrieb Michael Kelley:
From: Michael Kelley Sent: Thursday, September 4, 2025 10:36 PM
From: Thomas Zimmermann Sent: Thursday, September 4, 2025
7:56
Out of broad need for the register and bitfield macros in Rust, move
them out of nova into the kernel crate. Several usecases need them (Nova
is already using these and Tyr developers said they need them).
bitfield moved into kernel crate - defines bitfields in Rust.
register moved into io module
Add support for custom visiblity to allow for users to control visibility
of the structure and helpers.
Reviewed-by: Alexandre Courbot
Reviewed-by: Elle Rhumsaa
Signed-off-by: Joel Fernandes
---
drivers/gpu/nova-core/bitfield.rs| 49 +++-
drivers/gpu/nova-core/regs/
The bitfield macro's setter accesors currently uses the From trait for
type conversion, which is overly restrictive and prevents use cases such
as narrowing conversions (e.g., u8 struct storage size does not work
with 'as u32' for the field size).
Replace 'from' with 'as' in the setter implementat
The bitfield-specific into new macro. This will be used to define
structs with bitfields, similar to C language.
Reviewed-by: Elle Rhumsaa
Reviewed-by: Alexandre Courbot
Signed-off-by: Joel Fernandes
---
drivers/gpu/nova-core/bitfield.rs| 315 +++
drivers/gpu/nova-c
Add kernel-doc to xe_guc_submit.c describing the submission path,
the per-queue single-threaded model with pause/resume, the driver shadow
state machine and lost-H2G replay, job timeout handling, recovery flows
(GT reset, PM resume, VF resume), and reclaim constraints.
v2:
- Mirror tweaks for cla
This commit introduces core infrastructure for handling GSP command and
message queues in the nova-core driver. The command queue system enables
bidirectional communication between the host driver and GSP firmware
through a remote message passing interface.
The interface is based on passing serial
On Tue, Sep 30, 2025 at 12:43 AM Dmitry Baryshkov
wrote:
>
> On Tue, Sep 30, 2025 at 11:18:17AM +0530, Akhil P Oommen wrote:
> > A8x is the next generation of Adreno GPUs, featuring a significant
> > hardware design change. A major update to the design is the introduction
> > of Slice architecture
The vkms_crtc_atomic_check() function calls the deprecated
drm_atomic_get_existing_plane_state() helper for its internal mode
checking logic.
During atomic_check, the existing state is the new state and
drm_atomic_get_existing_plane_state() can thus be replaced by
drm_atomic_get_new_plane_state().
On 2025-09-30 03:07, Pekka Paalanen wrote:
On Thu, 14 Aug 2025 21:50:06 -0600
Alex Hung wrote:
From: Harry Wentland
Certain operations require us to preserve values below 0.0 and
above 1.0 (0x0 and 0x respectively in 16 bpc unorm). One
such operation is a BT709 encoding operation foll
On Tue Sep 30, 2025 at 9:36 AM JST, Alistair Popple wrote:
> On 2025-09-30 at 00:34 +1000, Alexandre Courbot wrote...
>> On Mon Sep 29, 2025 at 3:19 PM JST, Alistair Popple wrote:
>>
>> >> > +
>> >> > +/// Number of GSP pages making the Msgq.
>> >> > +pub(crate) const MSGQ_NUM_PAGES: u32 = 0x3f;
On 9/30/25 3:16 PM, Alistair Popple wrote:
> +impl GspRpcHeader {
> +pub(crate) fn new(cmd_size: u32, function: u32) -> Self {
> +Self(bindings::rpc_message_header_v {
> +// TODO: magic number
> +header_version: 0x0300,
> +signature: bindings::NV_
On 9/30/25 3:16 PM, Alistair Popple wrote:
> +// SAFETY: No DMA allocations have been made yet
> +unsafe { pdev.dma_set_mask_and_coherent(DmaMask::new::<47>())? };
I think you forgot to derive the value from the relevant sources, i.e. physical
bus, DMA controller and MMU capabiliti
On 9/30/25 3:16 PM, Alistair Popple wrote:
> Changes since v2:
>
> The main change since v2 has been to make all firmware bindings
> completely opaque. It has been made clear this is a pre-requisite for
> this series to progress upstream as it should make supporting
> different firmware versions e
In order to unify the handling of the panel and bridge, apply
panel_bridge helpers for Analogix DP driver. With this patch, the
bridge support will also become available.
The following changes have ben made:
- Apply plane_bridge helper to wrap the panel as the bridge.
- Remove the explicit panel A
Boot the GSP to the RISC-V active state. Completing the boot requires
running the CPU sequencer which will be added in a future commit.
Signed-off-by: Alistair Popple
Reviewed-by: Lyude Paul
---
Changes for v3:
- Fixed minor nit from John
- Added booter load error thanks to Timur's suggestio
From: Joel Fernandes
This will be needed by both the GSP boot code as well as GSP resume code
in the sequencer.
Signed-off-by: Joel Fernandes
Reviewed-by: Lyude Paul
---
drivers/gpu/nova-core/falcon.rs | 9 +
drivers/gpu/nova-core/regs.rs | 6 ++
2 files changed, 15 insertions(+
Add the RM registry and system information commands that enable the host
driver to configure GSP firmware parameters during initialization.
The RM registry is serialized into a packed format and sent via the
command queue. For now only two parameters which are required to boot
GSP are hardcoded. I
Adds bindings and constructors for PACKED_REGISTRY_TABLE and
PACKED_REGISTRY_ENTRY structures.
Signed-off-by: Alistair Popple
---
Changes for v3:
- New for v3
---
drivers/gpu/nova-core/gsp/fw/commands.rs | 40 +++
.../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 17 +++
Set the correct DMA mask. Without this DMA will fail on some setups.
Signed-off-by: Alistair Popple
---
Changes for v2:
- Update DMA mask to correct value for Ampere/Turing (47 bits)
---
drivers/gpu/nova-core/driver.rs | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git
From: Joel Fernandes
A data structure that can be used to write across multiple slices which
may be out of order in memory. This lets SBuffer user correctly and
safely write out of memory order, without error-prone tracking of
pointers/offsets.
let mut buf1 = [0u8; 3];
let mut buf2 = [0u8; 5];
The GSP requires some pieces of metadata to boot. These are passed in a
struct which the GSP transfers via DMA. Create this struct and get a
handle to it for future use when booting the GSP.
Signed-off-by: Alistair Popple
---
Changes for v3:
- Don't re-export WPR constants (thanks Alex)
Chang
Changes since v2:
The main change since v2 has been to make all firmware bindings
completely opaque. It has been made clear this is a pre-requisite for
this series to progress upstream as it should make supporting
different firmware versions easier in future.
Overall the extra constructors and ac
> -Original Message-
> From: Leon Romanovsky
> Sent: 30 September 2025 10:01
> To: Alex Williamson
> Cc: Jason Gunthorpe ; Andrew Morton foundation.org>; Bjorn Helgaas ; Christian König
> ; dri-devel@lists.freedesktop.org;
> io...@lists.linux.dev; Jens Axboe ; Joerg Roedel
> ; k...@vg
On Tue, Sep 30, 2025 at 11:18:13AM +0530, Akhil P Oommen wrote:
> Move MMU fault handler for each generation to adreno function list. This
> will help to use common code for mmu pagefault handler registration between
> a6x/a7x and a8x layer.
>
> Signed-off-by: Akhil P Oommen
> ---
> drivers/gpu/
When userptr is used on SVM-enabled VMs, a non-NULL
hmm_range::dev_private_owner value might mean that
hmm_range_fault() attempts to return device private pages.
Either that will fail, or the userptr code will not know
how to handle those.
Use NULL for hmm_range::dev_private_owner to migrate
such
On 2025-09-01 08:25, José Expósito wrote:
Hi everyone,
This series allow to configure one or more VKMS instances without having
to reload the driver using configfs.
The process of configuring a VKMS device is documented in "vkms.rst".
In addition, I created a CLI tool to easily control VKMS
On 9/25/25 20:11, David Hildenbrand wrote:
> On 16.09.25 14:21, Balbir Singh wrote:
>> Implement CPU fault handling for zone device THP entries through
>> do_huge_pmd_device_private(), enabling transparent migration of
>> device-private large pages back to system memory on CPU access.
>>
>> When th
On 9/24/25 01:56, Karim Manaouil wrote:
> On Tue, Sep 23, 2025 at 01:44:20PM +1000, Balbir Singh wrote:
>> On 9/23/25 12:23, Zi Yan wrote:
>>> On 16 Sep 2025, at 8:21, Balbir Singh wrote:
>>>
Extend migrate_vma_collect_pmd() to handle partially mapped large folios
that require splitting b
On Tue, Sep 30, 2025 at 1:42 PM Alistair Popple wrote:
>
> Thanks. Is it still expected that `#[allow(clippy::incompatible_msrv)]` is
> required? Just adding it to `rust_allowed_features` doesn't make the warning
> go
> away without the allow, but maybe I'm just doing something wrong...
The warn
On Tue, 30 Sep 2025 12:58:29 +0200
"Danilo Krummrich" wrote:
> On Tue Sep 30, 2025 at 12:12 PM CEST, Boris Brezillon wrote:
> > So, my take on that is that what we want ultimately is to have the
> > functionality provided by drm_sched split into different
> > components that can be used in isolat
On 2025-09-30 at 00:45 +1000, Alexandre Courbot wrote...
> On Mon Sep 29, 2025 at 11:38 PM JST, Miguel Ojeda wrote:
> > On Mon, Sep 29, 2025 at 4:34 PM Alexandre Courbot
> > wrote:
> >>
> >> I think you will also need to explicitly enable the feature somewhere -
> >> for the kernel crate it is i
This ARM architecture's source file does not require .
Remove the include statement.
Signed-off-by: Thomas Zimmermann
---
arch/arm/mach-pxa/spitz.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-pxa/spitz.h b/arch/arm/mach-pxa/spitz.h
index 04828d8918aa..873844194a31 100644
---
This is a note to let you know that I've just added the patch titled
drm/ast: Use msleep instead of mdelay for edid read
to the 6.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm
The ingenic CRTC atomic_enable() implementation will indirectly call
drm_atomic_get_private_obj_state() through ingenic_drm_get_priv_state().
drm_atomic_get_private_obj_state() will either return the new state for
the object in the global state if it exists, or will allocate a new one
and add it t
The ingenic IPU atomic_set_property implementation uses the deprecated
drm_atomic_get_existing_crtc_state() helper.
This hook is called during the state building process, before
atomic_check, and thus before the states are swapped. The existing state
thus points to the new state, and we can use
dr
While the old and new state pointers are somewhat self-explanatory, the
state pointer and its relation to the other two really isn't.
Now that we've cleaned up everything and it isn't used in any
modesetting path, we can document what it's still useful for: to free
the right state when we free the
The drm_atomic_get_existing_plane_state() function is deprecated and
isn't used anymore, so let's remove it.
Reviewed-by: Ville Syrjälä
Signed-off-by: Maxime Ripard
---
To: Maarten Lankhorst
To: Maxime Ripard
To: Thomas Zimmermann
To: David Airlie
To: Simona Vetter
Cc: dri-devel@lists.freed
In the tilcdc_crtc_atomic_check(), the tilcdc driver hand-crafts its own
implementation of drm_atomic_helper_check_crtc_primary_plane(). And it
does so by accessing the state pointer in drm_atomic_state->planes which
is deprecated.
Let's use the right helper here.
Reviewed-by: Ville Syrjälä
Acke
Hi,
Here's a series to get rid of the drm_atomic_helper_get_existing_*_state
accessors.
The initial intent was to remove the __drm_*_state->state pointer to
only rely on old and new states, but we still need it now to know which
of the two we need to free: if a state has not been committed (eithe
On Mon, 29 Sep 2025 22:03:15 +0200
Loïc Molinari wrote:
> Log the number of pages and their sizes actually mapped/unmapped by
> the IOMMU page table driver. Since a map/unmap op is often split in
> several ops depending on the underlying scatter/gather table, add the
> start address and the total
On Mon, 29 Sep 2025 22:03:14 +0200
Loïc Molinari wrote:
> Introduce the 'panthor.transparent_hugepage' boolean module parameter
> (false by default). When the parameter is set to true, a new tmpfs
> mount point is created and mounted using the 'huge=within_size'
> option. It's then used at GEM ob
On Tue Sep 30, 2025 at 11:00 AM CEST, Philipp Stanner wrote:
> +Cc Sima, Dave
>
> On Mon, 2025-09-29 at 16:07 +0200, Danilo Krummrich wrote:
>> On Wed Sep 3, 2025 at 5:23 PM CEST, Tvrtko Ursulin wrote:
>> > This is another respin of this old work^1 which since v7 is a total
>> > rewrite and
>> > c
When multiple bridges are present, EDID detection capability
(DRM_BRIDGE_OP_EDID) takes precedence over modes detection
(DRM_BRIDGE_OP_MODES). To ensure the above two capabilities are
determined by the last bridge in the chain, we handle three cases:
Case 1: The later bridge declares only DRM_BRID
If there is neither a panel nor a bridge, the display timing can be
parsed from the display-timings node under the dp node.
In order to get rid of &analogix_dp_plat_data.get_modes() and make
the codes more consistent, apply DRM legacy bridge to parse display
timings.
Signed-off-by: Damon Ding
-
Use &analogix_dp_plat_data.bridge instead of &exynos_dp_device.ptn_bridge
directly.
Signed-off-by: Damon Ding
Reviewed-by: Dmitry Baryshkov
Tested-by: Marek Szyprowski
--
Changes in v3:
- Fix the typographical error for &dp->plat_data.bridge.
Changes in v4:
- Rename the &analogix_dp_plat
As suggested by Dmitry, the DRM legacy bridge driver can be pulled
out of imx/ subdir for multi-platform use. The driver is also renamed
to make it more generic and suitable for platforms other than i.MX.
Additionally, a new API drm_bridge_is_legacy() is added to identify
the legacy bridge, allowi
On Mon, Sep 29, 2025 at 03:17:49PM -0600, Alex Williamson wrote:
> On Sun, 28 Sep 2025 17:50:20 +0300
> Leon Romanovsky wrote:
> > +static int validate_dmabuf_input(struct vfio_pci_core_device *vdev,
> > +struct vfio_device_feature_dma_buf *dma_buf,
> > +
+Cc Sima, Dave
On Mon, 2025-09-29 at 16:07 +0200, Danilo Krummrich wrote:
> On Wed Sep 3, 2025 at 5:23 PM CEST, Tvrtko Ursulin wrote:
> > This is another respin of this old work^1 which since v7 is a total rewrite
> > and
> > completely changes how the control is done.
>
> I only got some of the
Hello Tomeu Vizoso,
Commit 0810d5ad88a1 ("accel/rocket: Add job submission IOCTL") from
Jul 21, 2025 (linux-next), leads to the following Smatch static
checker warning:
drivers/accel/rocket/rocket_job.c:621 rocket_ioctl_submit()
warn: potential user controlled sizeof overflow 'i *
Add a DRM panel driver for the Tianma TL121BVMS07-00 12.1"
MIPI-DSI TFT LCD panel. The panel requires multiple power
supplies (AVDD, AVEE, 1.8V logic), an enable GPIO, and a
backlight device. The panel is based on the Ilitek IL79900A
controller.
Signed-off-by: Langyan Ye
---
.../drm/panel/panel-
On Tue, Sep 30, 2025 at 11:18:20AM +0530, Akhil P Oommen wrote:
> GMU lies on the CX domain and accesses CX GBIF. So do CX GBIF
> configurations before GMU wakes up. Also, move these registers to
> the catalog.
>
> Signed-off-by: Akhil P Oommen
Fixes tag?
> ---
> drivers/gpu/drm/msm/adreno/a6x
On Tue, Sep 30, 2025 at 12:05 AM Dmitry Baryshkov
wrote:
>
> On Tue, Sep 30, 2025 at 11:18:08AM +0530, Akhil P Oommen wrote:
> > PIPE enum definitions are backward compatible. So move its definition
> > to adreno_common.xml.
>
> What do you mean here by 'backward compatible'. Are they going to be
On Thu, 14 Aug 2025 21:50:06 -0600
Alex Hung wrote:
> From: Harry Wentland
>
> Certain operations require us to preserve values below 0.0 and
> above 1.0 (0x0 and 0x respectively in 16 bpc unorm). One
> such operation is a BT709 encoding operation followed by its
> decoding operation, or th
On Mon, Sep 29, 2025 at 03:00:04PM +0200, Maxime Ripard wrote:
> On Thu, Sep 25, 2025 at 05:16:07PM +0300, Dmitry Baryshkov wrote:
> > On Thu, Sep 25, 2025 at 03:13:47PM +0200, Maxime Ripard wrote:
> > > On Wed, Sep 10, 2025 at 06:26:56PM +0300, Dmitry Baryshkov wrote:
> > > > On Wed, Sep 10, 2025
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