MCIMX-LVDS1[1] display module integrates a HannStar HSD100PXN1 LVDS
display panel and a touch IC. Add an overlay to support the LVDS
panel on i.MX53 QSB / QSRB platforms.
[1] https://www.nxp.com/part/MCIMX-LVDS1
Signed-off-by: Liu Ying
---
I mark RFC in patch subject prefix because if the DT
. The pixel engine driver as a master binds
those unit drivers as components. While at it, the pixel engine
driver is a component to be bound with the upcoming DRM driver.
Signed-off-by: Liu Ying
---
v3:
* No change.
v2:
* Use OF alias id to get instance id.
drivers/gpu/drm/imx/dc/Makefile | 3
Enable display controller for i.MX8qxp MEK.
Signed-off-by: Liu Ying
---
v3:
* No change.
v2:
* New patch. (Francesco)
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
b/arch/arm64/boot/dts
MX8-DLVDS-LCD1 display module integrates a KOE TX26D202VM0BWA LCD panel
and a touch IC. Add an overlay to support the LCD panel on i.MX8qxp
MEK. mipi_lvds_0_ldb channel0 and mipi_lvds_1_ldb channel1 send odd
and even pixels to the panel respectively.
Signed-off-by: Liu Ying
---
v3:
* No change
Add myself as the maintainer of i.MX8qxp Display Controller.
Signed-off-by: Liu Ying
---
v3:
* No change.
v2:
* Improve file list. (Frank)
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 10bd3f40a2f1..fa82fdd9bfef 100644
The MIPI-LVDS combo subsystems are peripherals of pixel link MSI
bus in i.MX8qxp display controller subsystem. Add the MIPI-LVDS
combo subsystems.
Signed-off-by: Liu Ying
---
v3:
* No change.
v2:
* New patch. (Francesco)
.../boot/dts/freescale/imx8qxp-ss-dc.dtsi | 4 +
.../dts
Add display controller subsystem in i.MX8qxp SoC.
Signed-off-by: Liu Ying
---
v3:
* No change.
v2:
* New patch. (Krzysztof)
.../arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | 408 ++
.../boot/dts/freescale/imx8qxp-ss-dc.dtsi | 236 ++
arch/arm64/boot/dts/freescale
i.MX8qxp Display Controller(DC) is comprised of three main components that
include a blit engine for 2D graphics accelerations, display controller for
display output processing, as well as a command sequencer.
Signed-off-by: Liu Ying
---
v3:
* No change.
v2:
* Drop fsl,dc-*-id DT properties
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v3:
* Collect Rob's R-b tag.
v2:
* Drop unneeded "|". (Krzysztof)
.../fsl,imx8qxp-dc
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit. Add driver for it.
Signed-off-by: Liu Ying
---
v3:
* No change.
v2:
* No change.
drivers/gpu/drm/imx/dc/Kconfig | 1 +
drivers/gpu/drm/imx/dc/Makefile | 2 +-
drivers/gpu
assigned-clock* properties can be used by default now, so allow them.
Signed-off-by: Liu Ying
---
v3:
* No change.
v2:
* New patch as needed by MIPI/LVDS subsystems device tree.
.../devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml | 5 -
1 file changed, 5 deletions(-)
diff --git
i.MX8qxp Display Controller contains a command sequencer is designed to
autonomously process command lists.
Signed-off-by: Liu Ying
---
v3:
* New patch. (Rob)
.../imx/fsl,imx8qxp-dc-command-sequencer.yaml | 67 +++
1 file changed, 67 insertions(+)
create mode 100644
Document SCU controlled display pixel link child nodes.
Signed-off-by: Liu Ying
---
v3:
* No change.
v2:
* New patch as needed by display controller subsystem device tree.
.../devicetree/bindings/firmware/fsl,scu.yaml | 20 +++
1 file changed, 20 insertions(+)
diff --git
primary planes(backed by FetchLayer and FetchWarp respectively). The
registers of the display controller are accessed without command sequencer
involved, instead just by using CPU. The command sequencer is supposed to
be used by the blit engine.
Signed-off-by: Liu Ying
---
v3:
* No change.
v2
as components. While at it, the display engine driver
is a component to be bound with the upcoming DRM driver.
Signed-off-by: Liu Ying
---
v3:
* No change.
v2:
* Use OF alias id to get instance id.
* Add dev member to struct dc_tc.
drivers/gpu/drm/imx/Kconfig | 1 +
drivers/gpu/drm/imx/Makefile
i.MX8qxp Display Controller contains a AXI performance counter which allows
measurement of average bandwidth and latency during operation.
Signed-off-by: Liu Ying
---
v3:
* New patch. (Rob)
...sl,imx8qxp-dc-axi-performance-counter.yaml | 57 +++
1 file changed, 57 insertions
i.MX8qxp Display Controller pixel engine consists of all processing units
that operate in the AXI bus clock domain. Command sequencer and interrupt
controller of the Display Controller work with AXI bus clock, but they are
not in pixel engine.
Signed-off-by: Liu Ying
---
v3:
* No change.
v2
i.MX8qxp Display Controller display engine consists of all processing units
that operate in a display clock domain.
Signed-off-by: Liu Ying
---
v3:
* No change.
v2:
* Drop fsl,dc-*-id DT properties. (Krzysztof)
* Drop port property. (Krzysztof)
* Fix register range sizes in example.
.../imx
i.MX8qxp Display Controller contains a blit engine for raster graphics.
It may read up to 3 source images from memory and computes one destination
image from it, which is written back to memory.
Signed-off-by: Liu Ying
---
v3:
* New patch. (Rob)
.../imx/fsl,imx8qxp-dc-blit-engine.yaml
Freescale i.MX8qxp Display Controller is implemented as construction set of
building blocks with unified concept and standardized interfaces. Document
all existing processing units.
Signed-off-by: Liu Ying
---
v3:
* Combine fsl,imx8qxp-dc-fetchunit-common.yaml,
fsl,imx8qxp-dc-fetchlayer.yaml
display driver.
* Drop drm/drm_module.h include from dc-drv.c.
* Improve file list in MAINTAINERS. (Frank)
* Add entire i.MX8qxp display controller device tree for review. (Krzysztof)
* Add MIPI/LVDS subsystems device tree and a DT overlay for imx8qxp
MEK to test a LVDS panel as an example. (Francesco
On 07/23/2024, Rob Herring wrote:
> On Fri, Jul 12, 2024 at 05:32:38PM +0800, Liu Ying wrote:
>> assigned-clock* properties can be used by default now, so allow them.
>>
>> Signed-off-by: Liu Ying
>> ---
>> v2:
>> * New patch as needed by MIPI/LVDS
On 07/23/2024, Rob Herring wrote:
> On Fri, Jul 12, 2024 at 05:32:29PM +0800, Liu Ying wrote:
>> i.MX8qxp Display Controller display engine consists of all processing units
>> that operate in a display clock domain.
>>
>> Signed-off-by: Liu Ying
>> ---
>>
On 07/23/2024, Rob Herring wrote:
> On Fri, Jul 12, 2024 at 05:32:28PM +0800, Liu Ying wrote:
>> Freescale i.MX8qxp Display Controller is implemented as construction set of
>> building blocks with unified concept and standardized interfaces.
>>
>> Document some proc
MX8-DLVDS-LCD1 display module integrates a KOE TX26D202VM0BWA LCD panel
and a touch IC. Add an overlay to support the LCD panel on i.MX8qxp
MEK. mipi_lvds_0_ldb channel0 and mipi_lvds_1_ldb channel1 send odd
and even pixels to the panel respectively.
Signed-off-by: Liu Ying
---
v2:
* New patch
Enable display controller for i.MX8qxp MEK.
Signed-off-by: Liu Ying
---
v2:
* New patch. (Francesco)
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
b/arch/arm64/boot/dts/freescale/imx8qxp
The MIPI-LVDS combo subsystems are peripherals of pixel link MSI
bus in i.MX8qxp display controller subsystem. Add the MIPI-LVDS
combo subsystems.
Signed-off-by: Liu Ying
---
v2:
* New patch. (Francesco)
.../boot/dts/freescale/imx8qxp-ss-dc.dtsi | 4 +
.../dts/freescale/imx8qxp-ss-mipi
Add display controller subsystem in i.MX8qxp SoC.
Signed-off-by: Liu Ying
---
v2:
* New patch. (Krzysztof)
.../arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | 408 ++
.../boot/dts/freescale/imx8qxp-ss-dc.dtsi | 236 ++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi| 25
Document SCU controlled display pixel link child nodes.
Signed-off-by: Liu Ying
---
v2:
* New patch as needed by display controller subsystem device tree.
.../devicetree/bindings/firmware/fsl,scu.yaml | 20 +++
1 file changed, 20 insertions(+)
diff --git a/Documentation
assigned-clock* properties can be used by default now, so allow them.
Signed-off-by: Liu Ying
---
v2:
* New patch as needed by MIPI/LVDS subsystems device tree.
.../devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml | 5 -
1 file changed, 5 deletions(-)
diff --git a/Documentation
Add myself as the maintainer of i.MX8qxp Display Controller.
Signed-off-by: Liu Ying
---
v2:
* Improve file list. (Frank)
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 278c1ec148c1..487fb417fca7 100644
--- a/MAINTAINERS
+++ b
primary planes(backed by FetchLayer and FetchWarp respectively). The
registers of the display controller are accessed without command sequencer
involved, instead just by using CPU. The command sequencer is supposed to
be used by the blit engine.
Signed-off-by: Liu Ying
---
v2:
* Find next bridge
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit. Add driver for it.
Signed-off-by: Liu Ying
---
v2:
* No change.
drivers/gpu/drm/imx/dc/Kconfig | 1 +
drivers/gpu/drm/imx/dc/Makefile | 2 +-
drivers/gpu/drm/imx/dc/dc
. The pixel engine driver as a master binds
those unit drivers as components. While at it, the pixel engine
driver is a component to be bound with the upcoming DRM driver.
Signed-off-by: Liu Ying
---
v2:
* Use OF alias id to get instance id.
drivers/gpu/drm/imx/dc/Makefile | 3 +-
drivers/gpu/drm/imx
as components. While at it, the display engine driver
is a component to be bound with the upcoming DRM driver.
Signed-off-by: Liu Ying
---
v2:
* Use OF alias id to get instance id.
* Add dev member to struct dc_tc.
drivers/gpu/drm/imx/Kconfig | 1 +
drivers/gpu/drm/imx/Makefile| 1 +
drivers
i.MX8qxp Display Controller(DC) is comprised of three main components that
include a blit engine for 2D graphics accelerations, display controller for
display output processing, as well as a command sequencer.
Signed-off-by: Liu Ying
---
v2:
* Drop fsl,dc-*-id DT properties from example
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit.
Signed-off-by: Liu Ying
---
v2:
* Drop unneeded "|". (Krzysztof)
.../fsl,imx8qxp-dc-intc.yaml | 318 ++
1 file changed, 318
i.MX8qxp Display Controller pixel engine consists of all processing units
that operate in the AXI bus clock domain. Command sequencer and interrupt
controller of the Display Controller work with AXI bus clock, but they are
not in pixel engine.
Signed-off-by: Liu Ying
---
v2:
* Drop fsl,dc-*-id
i.MX8qxp Display Controller display engine consists of all processing units
that operate in a display clock domain.
Signed-off-by: Liu Ying
---
v2:
* Drop fsl,dc-*-id DT properties. (Krzysztof)
* Drop port property. (Krzysztof)
* Fix register range sizes in example.
.../imx/fsl,imx8qxp-dc
engine. FrameGen and TCon processing units are in display
engine.
Signed-off-by: Liu Ying
---
v2:
* Drop fsl,dc-*-id DT properties. (Krzysztof)
* Add port property to fsl,imx8qxp-dc-tcon.yaml. (Krzysztof)
* Fix register range sizes in examples.
.../imx/fsl,imx8qxp-dc-constframe.yaml| 44
rv.c.
* Improve file list in MAINTAINERS. (Frank)
* Add entire i.MX8qxp display controller device tree for review. (Krzysztof)
* Add MIPI/LVDS subsystems device tree and a DT overlay for imx8qxp
MEK to test a LVDS panel as an example. (Francesco)
Liu Ying (16):
dt-bindings: display: i
On 07/09/2024, Rob Herring wrote:
> On Mon, Jul 08, 2024 at 02:30:37PM +0800, Liu Ying wrote:
>> On 07/07/2024, Krzysztof Kozlowski wrote:
>>> On 05/07/2024 11:09, Liu Ying wrote:
>>>> Freescale i.MX8qxp Display Controller is implemented as construction set of
>
On 07/08/2024, Krzysztof Kozlowski wrote:
> On 08/07/2024 08:51, Liu Ying wrote:
>> On 07/07/2024, Krzysztof Kozlowski wrote:
>>> On 05/07/2024 11:09, Liu Ying wrote:
>>>> i.MX8qxp Display Controller has a built-in interrupt controller to support
>>>>
On 07/08/2024, Krzysztof Kozlowski wrote:
> On 08/07/2024 08:47, Liu Ying wrote:
>> On 07/07/2024, Krzysztof Kozlowski wrote:
>>> On 05/07/2024 11:09, Liu Ying wrote:
>>>> i.MX8qxp Display Controller pixel engine consists of all processing units
>>>>
On 07/05/2024, Francesco Dolcini wrote:
> Hello Liu,
Hello Francesco,
>
> On Fri, Jul 05, 2024 at 05:09:22PM +0800, Liu Ying wrote:
>> This patch series aims to add Freescale i.MX8qxp Display Controller support.
>
> I really appreciate your work here, I am looking
On 07/07/2024, Krzysztof Kozlowski wrote:
> On 05/07/2024 11:09, Liu Ying wrote:
>> i.MX8qxp Display Controller(DC) is comprised of three main components that
>> include a blit engine for 2D graphics accelerations, display controller for
>> display output processing, as well a
On 07/07/2024, Krzysztof Kozlowski wrote:
> On 05/07/2024 11:09, Liu Ying wrote:
>> i.MX8qxp Display Controller has a built-in interrupt controller to support
>> Enable/Status/Preset/Clear interrupt bit.
>>
>> Signed-off-by: Liu Ying
>> ---
>> .../fsl,imx8
On 07/07/2024, Krzysztof Kozlowski wrote:
> On 05/07/2024 11:09, Liu Ying wrote:
>> i.MX8qxp Display Controller pixel engine consists of all processing units
>> that operate in the AXI bus clock domain. Command sequencer and interrupt
>> controller of the Display Control
On 07/07/2024, Krzysztof Kozlowski wrote:
> On 05/07/2024 11:09, Liu Ying wrote:
>> i.MX8qxp Display Controller display engine consists of all processing units
>> that operate in a display clock domain.
>>
>> Signed-off-by: Liu Ying
>> ---
>> .../imx/fsl,
On 07/07/2024, Krzysztof Kozlowski wrote:
> On 05/07/2024 11:09, Liu Ying wrote:
>> Freescale i.MX8qxp Display Controller is implemented as construction set of
>> building blocks with unified concept and standardized interfaces.
>>
>> Document some processing units to
nd_vblank_event() to
hold event lock like many other drivers do.
https://elixir.bootlin.com/linux/v6.10-rc6/source/drivers/gpu/drm/drm_vblank.c#L1120
> https://elixir.bootlin.com/linux/v6.10-rc6/source/include/linux/spinlock.h#L574
>
> Regards,
> Markus
--
Regards,
Liu Ying
On 07/06/2024, Frank Li wrote:
> On Fri, Jul 05, 2024 at 05:09:32PM +0800, Liu Ying wrote:
>> Add myself as the maintainer of i.MX8qxp Display Controller.
>>
>> Signed-off-by: Liu Ying
>> ---
>> MAINTAINERS | 19 +++
>> 1 file cha
Add myself as the maintainer of i.MX8qxp Display Controller.
Signed-off-by: Liu Ying
---
MAINTAINERS | 19 +++
1 file changed, 19 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 35db18d26c11..29c9d52e74d1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7379,6 +7379,25
primary planes(backed by FetchLayer and FetchWarp respectively). The
registers of the display controller is accessed without command sequencer
involved, instead just by using CPU. The command sequencer is supposed to
be used by the blit engine.
Signed-off-by: Liu Ying
---
drivers/gpu/drm/imx/dc
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit. Add driver for it.
Signed-off-by: Liu Ying
---
drivers/gpu/drm/imx/dc/Kconfig | 1 +
drivers/gpu/drm/imx/dc/Makefile | 2 +-
drivers/gpu/drm/imx/dc/dc-drv.c | 1
. The pixel engine driver as a master binds
those unit drivers as components. While at it, the pixel engine
driver is a component to be bound with the upcoming DRM driver.
Signed-off-by: Liu Ying
---
drivers/gpu/drm/imx/dc/Makefile | 3 +-
drivers/gpu/drm/imx/dc/dc-cf.c | 158
as components. While at it, the display engine driver
is a component to be bound with the upcoming DRM driver.
Signed-off-by: Liu Ying
---
drivers/gpu/drm/imx/Kconfig | 1 +
drivers/gpu/drm/imx/Makefile| 1 +
drivers/gpu/drm/imx/dc/Kconfig | 5 +
drivers/gpu/drm/imx/dc/Makefile | 5
i.MX8qxp Display Controller(DC) is comprised of three main components that
include a blit engine for 2D graphics accelerations, display controller for
display output processing, as well as a command sequencer.
Signed-off-by: Liu Ying
---
.../bindings/display/imx/fsl,imx8qxp-dc.yaml | 243
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit.
Signed-off-by: Liu Ying
---
.../fsl,imx8qxp-dc-intc.yaml | 321 ++
1 file changed, 321 insertions(+)
create mode 100644
Documentation
i.MX8qxp Display Controller pixel engine consists of all processing units
that operate in the AXI bus clock domain. Command sequencer and interrupt
controller of the Display Controller work with AXI bus clock, but they are
not in pixel engine.
Signed-off-by: Liu Ying
---
.../imx/fsl,imx8qxp-dc
i.MX8qxp Display Controller display engine consists of all processing units
that operate in a display clock domain.
Signed-off-by: Liu Ying
---
.../imx/fsl,imx8qxp-dc-display-engine.yaml| 166 ++
1 file changed, 166 insertions(+)
create mode 100644
Documentation/devicetree
engine. FrameGen and TCon processing units are in display
engine.
Signed-off-by: Liu Ying
---
.../imx/fsl,imx8qxp-dc-constframe.yaml| 51 +++
.../display/imx/fsl,imx8qxp-dc-extdst.yaml| 79 +++
.../imx/fsl,imx8qxp-dc-fetchlayer.yaml| 37 ++
.../imx/fsl,imx8qxp
uot;DPU". "DPU" is only mentioned in the SoC block
diagram and represents the whole display subsystem which includes the display
controller and prefech engines, etc.
Liu Ying (10):
dt-bindings: display: imx: Add some i.MX8qxp Display Controller
processing units
dt-bindin
; val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
> + else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
> + val |= VID_MODE_TYPE_BURST;
If the precedence really needs to be swapped(which again doesn't
seem to be necessary), then change the precedence in
dw_mipi_dsi_get_hcomponent_lbcc() too, for the sake of consistency.
> else
> val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
>
--
Regards,
Liu Ying
KOE TX26D202VM0BWA panel spec indicates the DE signal is active high in
timing chart, so add DISPLAY_FLAGS_DE_HIGH flag in display timing flags.
This aligns display_timing with panel_desc.
Fixes: 8a07052440c2 ("drm/panel: simple: Add support for KOE TX26D202VM0BWA
panel")
Signed-off-by
On 05/29/2024, Alexander Stein wrote:
> Hi,
>
> Am Mittwoch, 29. Mai 2024, 09:50:24 CEST schrieb Liu Ying:
>> On 05/29/2024, Alexander Stein wrote:
>>> Although very unlike to occur (media_blk_ctrl needs 'syscon' compatible
>>> removed), it lines up with the ot
_regmap(np, true);
}
EXPORT_SYMBOL_GPL(syscon_node_to_regmap);
Regard,
Liu Ying
>
> Signed-off-by: Alexander Stein
> ---
> Changes in v2:
> * Removed unused variable
> * Added missing \n at end of string
>
> drivers/gpu/drm/bridge/imx/imx93-mipi-
"failed to get block ctrl regmap");
Missing \n.
And, a build warning:
drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c: In function ‘imx93_dsi_probe’:
drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c:837:13: warning: unused variable
‘ret’ [-Wunused-variable]
mark the respective IRQ status
>> accordingly, and delay the check until everything has been processed.
>>
>> This should guarantee the helper functions don't return prematurely
>> while still returning proper values of either IRQ_HANDLED or IRQ_NONE.
>>
>> Reported b
On 5/20/24 17:08, Dmitry Baryshkov wrote:
> On Mon, 20 May 2024 at 06:29, Liu Ying wrote:
>>
>> On 5/20/24 06:11, Dmitry Baryshkov wrote:
>>> On Thu, May 16, 2024 at 06:10:06PM +0800, Liu Ying wrote:
>>>> Commit f3d9683346d6 ("drm/bridge: adv7511:
On 5/20/24 06:11, Dmitry Baryshkov wrote:
> On Thu, May 16, 2024 at 06:10:06PM +0800, Liu Ying wrote:
>> Commit f3d9683346d6 ("drm/bridge: adv7511: Allow IRQ to share GPIO pins")
>> fails to consider the case where adv7511->i2c_main->irq is zero, i.e.,
&
On 5/16/24 20:36, Neil Armstrong wrote:
> On 16/05/2024 13:06, Aradhya Bhatia wrote:
>> Hi Liu,
>>
>> Thanks for reviewing the patch.
>>
>> On 16/05/24 07:49, Liu Ying wrote:
>>> On 5/15/24 17:51, Aradhya Bhatia wrote:
>>>> Add the Microtips T
s().
Fixes: f3d9683346d6 ("drm/bridge: adv7511: Allow IRQ to share GPIO pins")
Signed-off-by: Liu Ying
---
drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
b/drivers/gpu/drm
oads/spec/datasheetFile/2660/13-103HIEB0GA0-S_V1.0_20211206.pdf
>
> Signed-off-by: Aradhya Bhatia
> ---
> drivers/gpu/drm/panel/panel-simple.c | 32
> 1 file changed, 32 insertions(+)
Like my comments for patch 3/6, this panel is not simple enou
hich
don't comply with this binding, like RL, TB, STBYB and RESET.
Note this binding only allows compatible, ports, backlight,
enable-gpios and power-supply properties, nothing more.
Regards,
Liu Ying
> [2]:
> https://lincolntechsolutions.com/wp-content/uploads/2023/04/LCD185-101CT
linux.dev
> Cc: ker...@dh-electronics.com
> Cc: linux-arm-ker...@lists.infradead.org
> ---
> .../bindings/display/bridge/synopsys,dw-hdmi.yaml | 8
> .../devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml| 8
> 2 files changed, 8 insertions(+), 8 delet
.display-controller: error -EINVAL: Cannot
connect bridge
[2.274009] imx-lcdif 32e8.display-controller: probe with driver
imx-lcdif failed with error -22
Fixes: 14b3cdbd0e5b ("drm/bridge: adv7511: make it honour next bridge in DT")
Signed-off-by: Liu Ying
---
drivers/gpu/drm/brid
bridge attach functions are
called."
Regards,
Liu Ying
>
> Remove the redundant checking codes "if (!bridge->encoder) { ... }".
>
> Signed-off-by: Sui Jingfeng
> ---
> drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 5 -
> drivers/gpu/drm/bridge/im
KOE TX26D202VM0BWA panel spec indicates the DE signal is active high in
timing chart, so add DISPLAY_FLAGS_DE_HIGH flag in display timing flags.
This aligns display_timing with panel_desc.
Fixes: 8a07052440c2 ("drm/panel: simple: Add support for KOE TX26D202VM0BWA
panel")
Signed-off-by
ot;)
Fixes: 199cf07ebd2b ("drm/bridge: panel: Add a device link between drm device
and panel device")
Reported-by: Linus Walleij
Closes:
https://lore.kernel.org/lkml/cacrpkdagzxd6hbix7mvunjajtmepg00pp6+nj1p0jrfj-ar...@mail.gmail.com/T/
Tested-by: Linus Walleij
Signed-off-by: Liu Ying
Export device_is_dependent() since the drm_kms_helper module is starting
to use it.
Signed-off-by: Liu Ying
---
v2:
* Newly introduced as needed by patch 2.
drivers/base/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 67ba592afc77
ink.
Note that patch 2 is already in drm-misc/drm-misc-fixes and
drm-misc/for-linux-next-fixes. Patch 1 needs to be reviewed and picked up.
v2:
* Introduce patch 1 to export device_is_dependent() to modules as needed by
patch 2.
Liu Ying (2):
driver core: Export device_is_dependent() to modules
by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202311151746.f7u7dzbz-...@intel.com/
Signed-off-by: Liu Ying
---
v2:
* Initialize 'best_n' to UINT_MAX instead of zero. (Maxime)
drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletion
ot;)
Fixes: 199cf07ebd2b ("drm/bridge: panel: Add a device link between drm device
and panel device")
Reported-by: Linus Walleij
Closes:
https://lore.kernel.org/lkml/cacrpkdagzxd6hbix7mvunjajtmepg00pp6+nj1p0jrfj-ar...@mail.gmail.com/T/
Tested-by: Linus Walleij
Signed-off-by: Liu Ying
es:
https://lore.kernel.org/oe-kbuild-all/202311151746.f7u7dzbz-...@intel.com/
Signed-off-by: Liu Ying
---
drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c
b/drivers/gpu/drm/bridge/imx/
: Use pixel clock rate
to calculate lbcc")
Reported-by: Heiko Stübner
Closes: https://lore.kernel.org/linux-arm-kernel/5979575.UjTJXf6HLC@diego/T/#u
Tested-by: Heiko Stübner # px30 minievb with xinpeng
xpp055c272
Signed-off-by: Liu Ying
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-
Add myself as the maintainer of the i.MX8qxp DPU DRM driver.
Acked-by: Laurentiu Palcu
Signed-off-by: Liu Ying
---
v11->v14:
* No change.
v10->v11:
* Rebase upon v6.0-rc1.
v9->v10:
* Add Laurentiu's A-b tag.
v1->v9:
* No change.
MAINTAINERS | 9 +
1 file changed,
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v10->v14:
* No change.
v9->v10:
* Add Rob's R-b tag.
v8->v9:
* Reference 'interrupts-extended' schema instead of 'interrupts' to require
an additional
Artificially use 'plane' and 'old_plane_state' to avoid 'not used' warning.
The precedent has already been set by other macros in the same file.
Acked-by: Daniel Vetter
Signed-off-by: Liu Ying
---
v6->v14:
* No change.
v5->v6:
* Fix commit message typo - s/Artifically/Artificially/
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Gasket.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v4->v14:
* No change.
v3->v4:
* Improve compatible property by using enum instead of oneOf+const. (Rob)
* Add Rob's R-b tag.
v2->v3:
* No change.
v1->v
This patch adds bindings for i.MX8qxp/qm Display Processing Unit.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v7->v14:
* No change.
v6->v7:
* Add Rob's R-b tag back.
v5->v6:
* Use graph schema. So, drop Rob's R-b tag as review is needed.
v4->v5:
* No change.
v3-&g
Fix dt binding yamllint warnings.
* Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm in DPU's
dt binding documentation.
* Use new dt binding way to add clocks in the dt binding examples.
* Address several comments from Laurentiu on the DPU DRM patch.
Liu Ying (6):
dt-bindings: disp
i.MX93 MIPI DSI specific extensions.
Signed-off-by: Liu Ying
---
v2->v3:
* Select GENERIC_PHY to fix Kconfig warning for GENERIC_PHY_MIPI_DPHY
dependency.
v1->v2:
* Use dev_err_probe() to replace DRM_DEV_ERROR(). (Sam and Alexander)
* Use dev_*() to replace DRM_*(). (Sam)
* Fix build f
Freescale i.MX93 SoC embeds a Synopsys Designware MIPI DSI host
controller and a Synopsys Designware MIPI DPHY. Some configurations
and extensions to them are controlled by i.MX93 media blk-ctrl.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring
---
v2->v3:
* No change.
v1->v2:
* Add Rob
happen for
the 1920x1080p@60 video mode at least.
Signed-off-by: Liu Ying
Reviewed-by: Neil Armstrong
---
v2->v3:
* Add Neil's R-b tag from v1.
v1->v2:
* No change.
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/g
sum up
HSA, HBP, HFP and HDISPLAY.
This helps the case where Raydium RM67191 DSI panel is connected, since
it's video timing for hsync length is only 2 pixels and without this patch
the programmed value for DSI_VID_HSA_TIME is only 2 with 4 data lanes.
Signed-off-by: Liu Ying
Reviewed-by: N
video
mode.
Signed-off-by: Liu Ying
Reviewed-by: Neil Armstrong
---
v2->v3:
* Add Neil's R-b tag from v1.
v1->v2:
* No change.
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi
Vendor drivers may need to fixup mode due to pixel clock tree limitation,
so introduce the ->mode_fixup() callcack to struct dw_mipi_dsi_plat_data
and call it at atomic check stage if available.
Signed-off-by: Liu Ying
---
v1->v3:
* No change.
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.
.
Signed-off-by: Liu Ying
---
v1->v3:
* No change.
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 945d46a76995..ed9288a9c444 100
ormats through pdata->get_input_bus_fmts()
first. If it's unavailable, fall back to the only format - MEDIA_BUS_FMT_FIXED,
which matches the default behavior if ->atomic_get_input_bus_fmts() is not
implemented as ->atomic_get_input_bus_fmts()'s kerneldoc indicates.
Signed-off-by: Liu Y
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