This patch adds bindings for i.MX8qm/qxp pixel combiner.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* No change.
v2->v3:
* Add Rob's R-b tag.
v1->v2:
* Use graph sc
or a 36-bit output bus(12-bit per component) to a pixel link.
Reviewed-by: Robert Foss
Reviewed-by: Laurent Pinchart
Signed-off-by: Liu Ying
---
Robert, I keep your R-b tag from v5. Let me know if you want me to drop it, as
v6 contains a fix.
v7->v8:
* No change.
v6->v7:
* No change.
bus(12-bit per component) to a pixel link.
Reviewed-by: Robert Foss
Reviewed-by: Laurent Pinchart
Signed-off-by: Liu Ying
---
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* Add Laurent's R-b tag.
v4->v5:
* Add Robert's R-b tag.
v3->v4:
* No change.
v2->v3:
*
Avoid using companion_port OF node after putting it in
imx8qxp_ldb_parse_dt_companion() of i.MX8qxp LDB bridge driver.
* Drop unnecessary check for maximum available LDB channels from
i.MX8qm LDB bridge driver.
* Mention i.MX8qm/qxp LDB official name 'pixel mapper' in i.MX8qm/qxp LDB
bridge
Hi,
On Fri, 2022-04-22 at 19:24 +0200, Guido Günther wrote:
> Hi,
> On Tue, Apr 19, 2022 at 09:08:48AM +0800, Liu Ying wrote:
> > The Northwest Logic MIPI DSI host controller embedded in i.MX8qxp
> > works with a Mixel MIPI DPHY + LVDS PHY combo to support either
> > a MI
On Wed, 2022-04-20 at 13:00 +0530, Vinod Koul wrote:
> On 19-04-22, 09:08, Liu Ying wrote:
> > Hi,
> >
> > This is the v8 series to add i.MX8qxp LVDS PHY mode support for the
> > Mixel
> > PHY in the Freescale i.MX8qxp SoC.
> >
> > The Mixel PHY i
wed-by: Guido Günther
Signed-off-by: Liu Ying
---
v7->v8:
* No change.
v6->v7:
* Use marco instead of magic number for CCM and CA values.
* Suppress 'checkpatch --strict' warnings.
* Check !opts in mixel_dphy_configure().
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Add Gu
Add support for Mixel MIPI DPHY + LVDS PHY combo IP
as found on Freescale i.MX8qxp SoC.
Cc: Guido Günther
Cc: Kishon Vijay Abraham I
Cc: Vinod Koul
Cc: Rob Herring
Cc: NXP Linux Team
Reviewed-by: Rob Herring
Reviewed-by: Guido Günther
Signed-off-by: Liu Ying
---
v7->v8:
* No change.
Koul
Cc: Rob Herring
Cc: NXP Linux Team
Reviewed-by: Rob Herring
Reviewed-by: Guido Günther
Signed-off-by: Liu Ying
---
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Add Rob's and Guido's R-b tags.
v2->v3:
* Improve the 'clo
I
Cc: Vinod Koul
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v7->v8:
* Trivial kernel doc style fix - add '*'.
v6->v7:
* Update the year of copyright.
* Better variable explanation for bits_per_lane_and_dclk_cycle.
v5->v6:
* Rebase upon v5.17-rc1.
v4->v5:
* Align kern
: Robert Chiras
Cc: Martin Kepplinger
Cc: Andrzej Hajda
Cc: Neil Armstrong
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: David Airlie
Cc: Daniel Vetter
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v7->v8:
* Resend with Andrzej's and Jernej's mail addressed updated.
v6-
PHY dt binding.
v1->v2:
* Convert mixel,mipi-dsi-phy plain text dt binding to json-schema. (Guido)
* Print invalid PHY mode in dmesg from the Mixel PHY driver. (Guido)
* Add Guido's R-b tag on the patch for the nwl-dsi drm bridge driver.
Liu Ying (5):
drm/bridge: nwl-dsi: Set PHY mode in nw
wed-by: Guido Günther
Signed-off-by: Liu Ying
---
v7->v8:
* No change.
v6->v7:
* Use marco instead of magic number for CCM and CA values.
* Suppress 'checkpatch --strict' warnings.
* Check !opts in mixel_dphy_configure().
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Add Gu
Add support for Mixel MIPI DPHY + LVDS PHY combo IP
as found on Freescale i.MX8qxp SoC.
Cc: Guido Günther
Cc: Kishon Vijay Abraham I
Cc: Vinod Koul
Cc: Rob Herring
Cc: NXP Linux Team
Reviewed-by: Rob Herring
Reviewed-by: Guido Günther
Signed-off-by: Liu Ying
---
v7->v8:
* No change.
Koul
Cc: Rob Herring
Cc: NXP Linux Team
Reviewed-by: Rob Herring
Reviewed-by: Guido Günther
Signed-off-by: Liu Ying
---
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Add Rob's and Guido's R-b tags.
v2->v3:
* Improve the 'clo
I
Cc: Vinod Koul
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v7->v8:
* Trivial kernel doc style fix - add '*'.
v6->v7:
* Update the year of copyright.
* Better variable explanation for bits_per_lane_and_dclk_cycle.
v5->v6:
* Rebase upon v5.17-rc1.
v4->v5:
* Align kern
: Robert Chiras
Cc: Martin Kepplinger
Cc: Andrzej Hajda
Cc: Neil Armstrong
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: David Airlie
Cc: Daniel Vetter
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* Rebase the se
ain text dt binding to json-schema. (Guido)
* Print invalid PHY mode in dmesg from the Mixel PHY driver. (Guido)
* Add Guido's R-b tag on the patch for the nwl-dsi drm bridge driver.
Liu Ying (5):
drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_mode_set()
phy: Add LVDS configuration options
dt-b
wed-by: Guido Günther
Signed-off-by: Liu Ying
---
v6->v7:
* Use marco instead of magic number for CCM and CA values.
* Suppress 'checkpatch --strict' warnings.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Add Guido's R-b tag.
v2->v3:
* Improve readability of mixel_dphy_set_m
Add support for Mixel MIPI DPHY + LVDS PHY combo IP
as found on Freescale i.MX8qxp SoC.
Cc: Guido Günther
Cc: Kishon Vijay Abraham I
Cc: Vinod Koul
Cc: Rob Herring
Cc: NXP Linux Team
Reviewed-by: Rob Herring
Reviewed-by: Guido Günther
Signed-off-by: Liu Ying
---
v6->v7:
* No change.
Koul
Cc: Rob Herring
Cc: NXP Linux Team
Reviewed-by: Rob Herring
Reviewed-by: Guido Günther
Signed-off-by: Liu Ying
---
v6->v7:
* No change.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Add Rob's and Guido's R-b tags.
v2->v3:
* Improve the 'clock-names' property by
I
Cc: Vinod Koul
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v6->v7:
* Update the year of copyright.
* Better variable explaination for bits_per_lane_and_dclk_cycle.
v5->v6:
* Rebase upon v5.17-rc1.
v4->v5:
* Align kernel-doc style to include/linux/phy/phy.h. (Vinod)
* Trivi
: Robert Chiras
Cc: Martin Kepplinger
Cc: Andrzej Hajda
Cc: Neil Armstrong
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: David Airlie
Cc: Daniel Vetter
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v6->v7:
* No change.
v5->v6:
* Rebase the series upon v5.17-rc1.
* Set PH
in dmesg from the Mixel PHY driver. (Guido)
* Add Guido's R-b tag on the patch for the nwl-dsi drm bridge driver.
Liu Ying (5):
drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_mode_set()
phy: Add LVDS configuration options
dt-bindings: phy: Convert mixel,mipi-dsi-phy to json-schema
dt-bindin
On Thu, 2022-04-14 at 11:07 +0530, Vinod Koul wrote:
> On 13-04-22, 20:39, Liu Ying wrote:
> > On Wed, 2022-04-13 at 16:19 +0530, Vinod Koul wrote:
> > > On 13-04-22, 18:04, Liu Ying wrote:
> > > > Hi Vinod,
> > > >
> > > > On Wed, 2022-04-1
On Wed, 2022-04-13 at 16:19 +0530, Vinod Koul wrote:
> On 13-04-22, 18:04, Liu Ying wrote:
> > Hi Vinod,
> >
> > On Wed, 2022-04-13 at 11:41 +0530, Vinod Koul wrote:
> > > On 02-04-22, 13:24, Liu Ying wrote:
> > > > This patch allows LVDS PHYs to
Hi Vinod,
On Wed, 2022-04-13 at 11:51 +0530, Vinod Koul wrote:
> On 02-04-22, 13:24, Liu Ying wrote:
> > i.MX8qxp SoC embeds a Mixel MIPI DPHY + LVDS PHY combo which
> > supports
> > either a MIPI DSI display or a LVDS display. The PHY mode is
> > controlled
> &g
Hi Vinod,
On Wed, 2022-04-13 at 11:41 +0530, Vinod Koul wrote:
> On 02-04-22, 13:24, Liu Ying wrote:
> > This patch allows LVDS PHYs to be configured through
> > the generic functions and through a custom structure
> > added to the generic union.
> >
> > Th
Add myself as the maintainer of the i.MX8qxp DPU DRM driver.
Acked-by: Laurentiu Palcu
Signed-off-by: Liu Ying
---
v9->v10:
* Add Laurentiu's A-b tag.
v8->v9:
* No change.
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
Artificially use 'plane' and 'old_plane_state' to avoid 'not used' warning.
The precedent has already been set by other macros in the same file.
Acked-by: Daniel Vetter
Signed-off-by: Liu Ying
---
v9->v10:
* No change.
v8->v9:
* No change.
v7->v8:
* No change.
v6->v7:
* No cha
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v9->v10:
* Add Rob's R-b tag.
v8->v9:
* Reference 'interrupts-extended' schema instead of 'interrupts' to require
an additional interrupt(r_rtram_stall) b
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Gasket.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v9->v10:
* No change.
v8->v9:
* No change.
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
This patch adds bindings for i.MX8qxp/qm Display Processing Unit.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v9->v10:
* No change.
v8->v9:
* No change.
v7->v8:
* No change.
v6->v7:
* Add Rob's R-b tag back.
v5->v6:
* Use graph schema. So, drop Rob's R-b tag as r
he dt binding examples.
* Address several comments from Laurentiu on the DPU DRM patch.
Liu Ying (6):
dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding
dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding
drm/atomic: Avoi
wed-by: Guido Günther
Signed-off-by: Liu Ying
---
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Add Guido's R-b tag.
v2->v3:
* Improve readability of mixel_dphy_set_mode(). (Guido)
v1->v2:
* Print invalid PHY mode in dmesg. (Guido)
.../phy/freescale/phy-fsl-imx8-mi
Add support for Mixel MIPI DPHY + LVDS PHY combo IP
as found on Freescale i.MX8qxp SoC.
Cc: Guido Günther
Cc: Kishon Vijay Abraham I
Cc: Vinod Koul
Cc: Rob Herring
Cc: NXP Linux Team
Reviewed-by: Rob Herring
Reviewed-by: Guido Günther
Signed-off-by: Liu Ying
---
v5->v6:
* No change.
Koul
Cc: Rob Herring
Cc: NXP Linux Team
Reviewed-by: Rob Herring
Reviewed-by: Guido Günther
Signed-off-by: Liu Ying
---
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Add Rob's and Guido's R-b tags.
v2->v3:
* Improve the 'clock-names' property by dropping 'items:'.
v1-
I
Cc: Vinod Koul
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v5->v6:
* Rebase upon v5.17-rc1.
v4->v5:
* Align kernel-doc style to include/linux/phy/phy.h. (Vinod)
* Trivial tweaks.
* Drop Robert's R-b tag.
v3->v4:
* Add Robert's R-b tag.
v2->v3:
* No change.
v1->
: Robert Chiras
Cc: Martin Kepplinger
Cc: Andrzej Hajda
Cc: Neil Armstrong
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: David Airlie
Cc: Daniel Vetter
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v5->v6:
* Rebase the series upon v5.17-rc1.
* Set PHY mode in ->mo
PHY driver. (Guido)
* Improve the 'clock-names' property in the PHY dt binding.
v1->v2:
* Convert mixel,mipi-dsi-phy plain text dt binding to json-schema. (Guido)
* Print invalid PHY mode in dmesg from the Mixel PHY driver. (Guido)
* Add Guido's R-b tag on the patch for the nwl-dsi drm bridge
wed-by: Guido Günther
Signed-off-by: Liu Ying
---
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Add Guido's R-b tag.
v2->v3:
* Improve readability of mixel_dphy_set_mode(). (Guido)
v1->v2:
* Print invalid PHY mode in dmesg. (Guido)
.../phy/freescale/phy-fsl-imx8-mi
Add support for Mixel MIPI DPHY + LVDS PHY combo IP
as found on Freescale i.MX8qxp SoC.
Cc: Guido Günther
Cc: Kishon Vijay Abraham I
Cc: Vinod Koul
Cc: Rob Herring
Cc: NXP Linux Team
Reviewed-by: Rob Herring
Reviewed-by: Guido Günther
Signed-off-by: Liu Ying
---
v5->v6:
* No change.
Koul
Cc: Rob Herring
Cc: NXP Linux Team
Reviewed-by: Rob Herring
Reviewed-by: Guido Günther
Signed-off-by: Liu Ying
---
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Add Rob's and Guido's R-b tags.
v2->v3:
* Improve the 'clock-names' property by dropping 'items:'.
v1-
I
Cc: Vinod Koul
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v5->v6:
* Rebase upon v5.17-rc1.
v4->v5:
* Align kernel-doc style to include/linux/phy/phy.h. (Vinod)
* Trivial tweaks.
* Drop Robert's R-b tag.
v3->v4:
* Add Robert's R-b tag.
v2->v3:
* No change.
v1->
: Robert Chiras
Cc: Martin Kepplinger
Cc: Andrzej Hajda
Cc: Neil Armstrong
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: David Airlie
Cc: Daniel Vetter
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v5->v6:
* Rebase the series upon v5.17-rc1.
* Set PHY mode in ->mo
t;v2:
* Convert mixel,mipi-dsi-phy plain text dt binding to json-schema. (Guido)
* Print invalid PHY mode in dmesg from the Mixel PHY driver. (Guido)
* Add Guido's R-b tag on the patch for the nwl-dsi drm bridge driver.
Liu Ying (5):
drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_mode_set()
phy: A
n call. As nwl_dsi_bridge_detach() only calls
drm_of_panel_bridge_remove(), it can also be dropped.
Cc: Robert Foss
Cc: Guido Günther
Cc: Jagan Teki
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
drivers/gpu/drm/bridge/nwl-dsi.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/bridge/nwl-d
Hi Kishon, Vinod,
On Thu, 2021-06-10 at 17:38 +0800, Liu Ying wrote:
> Hi Kishon, Vinod,
>
> Any follow-up comments/suggestions based on my previous reply?
> Or, perhaps, just keep the patch as-is to support the generic lvds
> phy
> configuration structure?
Ping... Any
On Thu, 2022-03-17 at 18:58 +0100, José Expósito wrote:
> The function "drm_of_find_panel_or_bridge" has been deprecated in
> favor of "devm_drm_of_get_bridge".
>
> Switch to the new function and reduce boilerplate.
>
> Signed-off-by: José Expósito
On Mon, 2022-02-07 at 13:46 +0800, Liu Ying wrote:
> If the CRTC state is already inactive, it doesn't make sense to trigger
> the entry timer for self refresh work to make the display enter self
> refresh mode, because the disabled CRTC hints that either the entire
> display pipeline
On Thu, 2022-03-03 at 09:19 +0100, Lucas Stach wrote:
> Am Donnerstag, dem 03.03.2022 um 10:54 +0800 schrieb Liu Ying:
> > On Wed, 2022-03-02 at 12:57 +0100, Lucas Stach wrote:
> > > Am Mittwoch, dem 02.03.2022 um 17:41 +0800 schrieb Liu Ying:
> > > > On Wed, 2022-03-
On Wed, 2022-03-02 at 12:57 +0100, Lucas Stach wrote:
> Am Mittwoch, dem 02.03.2022 um 17:41 +0800 schrieb Liu Ying:
> > On Wed, 2022-03-02 at 10:23 +0100, Lucas Stach wrote:
> > > Am Mittwoch, dem 02.03.2022 um 03:54 +0100 schrieb Marek Vasut:
> > > > On 3
DIF, why not either leave the driver as one or split the common code
> > > > into its own driver like lcdif-common and then have smaller drivers
> > > > that handle their specific variations.
> > >
> > > I don't know exactly how the standalone driver looks like, but
idge);
> - if (ret)
> - return ret;
> + panel_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node,
> + 1, 0);
> + if (IS_ERR(panel_bridge))
> + return PTR_ERR(panel_bridge);
Now tha
t; to
> reflect the intended hardware state, but it also is a little
> over-specific. We want to make a transition through "disabled" any
> time we're exiting PSR at the same time as a CRTC switch.
Cool. I don't see any particular issue regarding the drop.
Liu Ying
> (
On Mon, 2022-02-28 at 16:34 +0100, Marek Vasut wrote:
> On 2/28/22 09:18, Liu Ying wrote:
>
> Hi,
Hi,
>
> > > > On Mon, 2022-02-28 at 01:45 +0100, Marek Vasut wrote:
> > > > > Add compatible string for i.MX8MP LCDIF variant. This is called
> &
ate->crtc)
> + return true;
I think 'new_state->enable' should be changed to 'new_state->active',
because 'active' is the one to enable/disable the CRTC while 'enable'
reflects whether a mode blob is set to CRTC state. The overall logic
added above is ok to me. Let's see if oth
On Mon, 2022-02-28 at 07:57 +0100, Marek Vasut wrote:
> On 2/28/22 07:37, Liu Ying wrote:
> > Hi Marek,
>
> Hi,
>
> > On Mon, 2022-02-28 at 01:45 +0100, Marek Vasut wrote:
> > > Add compatible string for i.MX8MP LCDIF variant. This is called LCDIFv3
>
Even if LCDIFv3 is covered by this dt-binding(which is obviously not
the case), 'fsl,imx8mp-lcdif' should be after 'fsl,imx6x-lcdif' as an
enum, otherwise LCDIFv3 is compatible to LCDIF.
Regards,
Liu Ying
>- fsl,imx8mq-lcdif
>- const: fsl,imx6sx-lcdif
>
Hi Philipp,
On Fri, 2022-01-28 at 17:19 +0800, Liu Ying wrote:
> In dw_hdmi_imx_probe(), if error happens after dw_hdmi_probe() returns
> successfully, dw_hdmi_remove() should be called where necessary as
> bailout.
>
> Fixes: c805ec7eb210 ("drm/imx: dw_hdmi-imx: move initi
To initialize register NWL_DSI_IRQ_MASK, it's enough to write it
only once in function nwl_dsi_init_interrupts().
Signed-off-by: Liu Ying
---
drivers/gpu/drm/bridge/nwl-dsi.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b
On Tue, 2022-02-08 at 11:02 +0100, Marek Vasut wrote:
> On 2/8/22 03:41, Liu Ying wrote:
>
> Hello everyone,
>
> > > > > There are many blank areas which are undocumented, this LCDIF
> > > > > CRC32
> > > > > feature, i.MX8M M
Hello Laurent,
On Tue, 2022-02-08 at 05:03 +0200, Laurent Pinchart wrote:
> Hello Liu Ying,
>
> On Tue, Feb 08, 2022 at 10:41:59AM +0800, Liu Ying wrote:
> > On Mon, 2022-02-07 at 11:43 +0100, Marek Vasut wrote:
> > > On 2/7/22 10:18, Liu Ying wrote:
> > > > &
On Mon, 2022-02-07 at 11:43 +0100, Marek Vasut wrote:
> On 2/7/22 10:18, Liu Ying wrote:
>
> Hi,
>
> > > > On Sun, 2022-02-06 at 19:56 +0100, Marek Vasut wrote:
> > > > > The LCDIF controller as present in i.MX6SX/i.MX8M Mini/Nano
> > > > &
On Mon, 2022-02-07 at 09:14 +0100, Marek Vasut wrote:
> On 2/7/22 06:13, Liu Ying wrote:
> > Hi Marek,
>
> Hi,
>
> > On Sun, 2022-02-06 at 19:56 +0100, Marek Vasut wrote:
> > > The LCDIF controller as present in i.MX6SX/i.MX8M Mini/Nano has a
> > > CRC
refresh work(the CRTC is disabled, while the relevant encoder
and bridges could be disabled or not depending on the drivers).
Cc: Rob Clark
Cc: Sean Paul
Cc: Zain Wang
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
Signed-off-by: Liu Ying
uct device_attribute *attr,
> + char *buf)
> +{
> + struct drm_device *drm = dev_get_drvdata(dev);
> + struct mxsfb_drm_private *mxsfb = drm->dev_private;
> + u32 hwcrc = readl(mxsfb->base, LCDC_V4_CRC_STAT);
Acc
wn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
drivers/gpu/drm/imx/dw_hdmi-imx.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c
b/drivers/gpu/drm/imx/dw_hdmi-i
bert Foss
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: David Airlie
Cc: Daniel Vetter
Cc: Kishon Vijay Abraham I
Cc: Vinod Koul
Cc: Kevin Hilman
Cc: Jerome Brunet
Cc: Martin Blumenstingl
Cc: Heiko Stuebner
Cc: Maxime Ripard
Cc: Guido Günther
Cc: Wyon Bi
Tested-by: Liu Yi
inod Koul
Cc: Kevin Hilman
Cc: Jerome Brunet
Cc: Martin Blumenstingl
Cc: Heiko Stuebner
Cc: Maxime Ripard
Cc: Guido Günther
Cc: Wyon Bi
Tested-by: Liu Ying # RM67191 DSI panel on i.MX8mq EVK
Reviewed-by: Andrzej Hajda
Reviewed-by: Neil Armstrong # for
phy-meson-axg-mipi-dphy.c
Te
Hi Laurent,
On Mon, 2022-01-24 at 00:15 +0200, Laurent Pinchart wrote:
> Hi Liu,
>
> Thank you for the patch.
Thank you for your review.
>
> On Wed, Jan 19, 2022 at 10:37:14AM +0800, Liu Ying wrote:
> > The D-PHY specification (v1.2) explicitly mentions that the T-CLK-PRE
Hi Heiko, Wyon,
On Wed, 2022-01-19 at 10:37 +0800, Liu Ying wrote:
> The D-PHY specification (v1.2) explicitly mentions that the T-CLK-PRE
> parameter's unit is Unit Interval(UI) and the minimum value is 8. Also,
> kernel doc of the 'clk_pre' member of struct phy_configure_opts_
Hi Neil,
On Wed, 2022-01-19 at 10:11 +0100, Neil Armstrong wrote:
> On 19/01/2022 09:40, Neil Armstrong wrote:
> > Hi,
> >
> > On 19/01/2022 03:37, Liu Ying wrote:
> > > The D-PHY specification (v1.2) explicitly mentions that the T-CLK-PRE
> > &g
inod Koul
Cc: Kevin Hilman
Cc: Jerome Brunet
Cc: Martin Blumenstingl
Cc: Heiko Stuebner
Cc: Maxime Ripard
Cc: Guido Günther
Tested-by: Liu Ying # RM67191 DSI panel on i.MX8mq EVK
Signed-off-by: Liu Ying
---
v1->v2:
* Use BITS_PER_BYTE macro. (Andrzej)
* Drop dsi argument from ui2b
Hi Andrzej,
Thanks for your review.
On Tue, 2022-01-18 at 10:24 +0100, Andrzej Hajda wrote:
> Hi,
>
> On 18.01.2022 03:59, Liu Ying wrote:
> > The D-PHY specification (v1.2) explicitly mentions that the T-CLK-PRE
> > parameter's unit is Unit Interval(UI) and the mini
Vijay Abraham I
Cc: Vinod Koul
Cc: Kevin Hilman
Cc: Jerome Brunet
Cc: Martin Blumenstingl
Cc: Heiko Stuebner
Cc: Maxime Ripard
Cc: Guido Günther
Tested-by: Liu Ying # RM67191 DSI panel on i.MX8mq EVK
Signed-off-by: Liu Ying
---
drivers/gpu/drm/bridge/nwl-dsi.c | 7 ++-
refresh work(the CRTC is disabled, while the relevant encoder
and bridges could be disabled or not depending on the drivers).
Cc: Rob Clark
Cc: Sean Paul
Cc: Zain Wang
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
Signed-off-by: Liu Ying
On Fri, 2022-01-07 at 14:53 -0500, Alex Deucher wrote:
> On Wed, Dec 29, 2021 at 11:07 PM Liu Ying wrote:
> >
> > Actual hardware state of CRTC is controlled by the member 'active'
> > in
> > struct drm_crtc_state instead of the member 'enable', according to
> >
efresh mode in
drivers")
Cc: Sean Paul
Cc: Rob Clark
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
Signed-off-by: Liu Ying
---
drivers/gpu/drm/drm_atomic_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Hi Kishon, Vinod,
Any follow-up comments/suggestions based on my previous reply?
Or, perhaps, just keep the patch as-is to support the generic lvds phy
configuration structure?
Thanks,
Liu Ying
On Thu, 2021-04-01 at 16:36 +0800, Liu Ying wrote:
> Hi Kishon,
>
> First of all, thanks
The file name for simple framebuffers' drm driver should be
'simpledrm.c' rather than 'simplekms.c'. This patch fixes it.
Signed-off-by: Liu Ying
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4d10ad6586042..7a9879c14742b
sc-next.
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=885811372fe101c4299c53eecc9fee72cf927a0c
I also see Guido's R-b and T-b tags on this series, though they comes
after Neil's push perhaps.
Thanks,
Liu Ying
>
> On Fri, 23 Apr 2021 at 11:42, Liu Ying wrote:
> > This
Hi Neil,
On Thu, 2021-04-22 at 14:07 +0200, Neil Armstrong wrote:
> Hi,
>
> On 22/04/2021 11:31, Liu Ying wrote:
> > Hi Neil,
> >
> > On Thu, 2021-04-22 at 10:48 +0200, Neil Armstrong wrote:
> > > Hi,
> > >
> > > On 22/04/2021 07:14, Li
Cc: Robert Foss
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: David Airlie
Cc: Daniel Vetter
Cc: Guido Günther
Cc: Robert Chiras
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v2->v3:
* Split some changes to patch 1/3 and 2/3, to clarify changes. (Neil)
v1->v2:
*
Cc: Robert Chiras
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v2->v3:
* Split from the single patch in v2 to clarify changes. (Neil)
drivers/gpu/drm/bridge/nwl-dsi.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/
and PHY are brought up and taken down
in pairs.
3) Patch 3/3 shifts the bridge operation as the last step.
v2->v3:
* Split the single patch in v2 into 3 patches. (Neil)
v1->v2:
* Fix a typo in commit message - s/unchange/unchanged/
Liu Ying (3):
drm/bridge: nwl-dsi: Force a full mod
g
Cc: Robert Foss
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: David Airlie
Cc: Daniel Vetter
Cc: Guido Günther
Cc: Robert Chiras
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v2->v3:
* Split from the single patch in v2 to clarify changes. (Neil)
dri
Hi Neil,
On Thu, 2021-04-22 at 10:48 +0200, Neil Armstrong wrote:
> Hi,
>
> On 22/04/2021 07:14, Liu Ying wrote:
> > Some MIPI DSI panel drivers like 'raydium,rm68200' send
> > MIPI_DCS_SET_DISPLAY_ON commands in panel_funcs->prepare(), which
> > requires t
ej Skrabec
Cc: David Airlie
Cc: Daniel Vetter
Cc: Guido Günther
Cc: Robert Chiras
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v1->v2:
* Fix commit message typo - s/unchange/unchanged/
drivers/gpu/drm/bridge/nwl-dsi.c | 86 +---
1 file changed, 46 inser
: Daniel Vetter
Signed-off-by: Liu Ying
---
drivers/gpu/drm/panel/panel-lvds.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-lvds.c
b/drivers/gpu/drm/panel/panel-lvds.c
index 59a8d99..19f11fa 100644
--- a/drivers/gpu/drm/panel/panel-lvds.c
krabec
Cc: David Airlie
Cc: Daniel Vetter
Cc: Guido Günther
Cc: Robert Chiras
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
drivers/gpu/drm/bridge/nwl-dsi.c | 86 +---
1 file changed, 46 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/bridge/nwl-ds
Hauer
> > > > Cc: Pengutronix Kernel Team
> > > > Cc: Fabio Estevam
> > > > Cc: NXP Linux Team
> > > > Cc: linux-arm-ker...@lists.infradead.org
> > > > ---
> > > > drivers/gpu/drm/imx/dcss/dcss-kms.c | 1 -
> >
On Wed, 2021-03-31 at 08:40 -0500, Rob Herring wrote:
> On Wed, 31 Mar 2021 14:33:18 +0800, Liu Ying wrote:
> > This patch adds bindings for i.MX8qm/qxp Control and Status Registers
> > module.
> >
> > Reviewed-by: Rob Herring
> > Signed-off-by: Liu Ying
> &
Hi Kishon,
First of all, thanks for your review.
On Wed, 2021-03-31 at 19:02 +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On 25/03/21 2:30 pm, Liu Ying wrote:
> > This patch allows LVDS PHYs to be configured through
> > the generic functions and through a custo
Add myself as the maintainer of DRM bridge drivers for i.MX SoCs.
Reviewed-by: Robert Foss
Signed-off-by: Liu Ying
---
v6->v7:
* Add Robert's R-b tag.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* No change.
MAINTAINERS
Reviewed-by: Robert Foss
Signed-off-by: Liu Ying
---
Note that this patch depends on the patch 'phy: Add LVDS configuration options',
which has already been sent with the following series to add Mixel combo PHY
found in i.MX8qxp:
https://www.spinics.net/lists/devicetree/msg414149.html
Marcel, I
supports the LDB single mode and split mode.
Tested-by: Marcel Ziswiler # Colibri iMX8X,
LT170410-2WHC, LP156WF1
Reviewed-by: Robert Foss
Signed-off-by: Liu Ying
---
Note that this patch depends on the patch 'phy: Add LVDS configuration options',
which has already been sent with the following series
This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v6->v7:
* No change.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Add Rob's R-b tag.
v2->v3:
* Drop 'fsl,syscon' property. (Rob)
* Mention the CSR
-by: Liu Ying
---
Marcel, I add your T-b tag from v6, let me know if you want me to drop it, as
the checkpatch fix in v7 is trivial.
v6->v7:
* Fix below complaints from 'checkpatch.pl --strict'. (Robert)
- 'Alignment should match open parenthesis'
- 'Prefer using the BIT macro'
*
codings between those modules. The PXL2DPI is purely
combinatorial.
Tested-by: Marcel Ziswiler # Colibri iMX8X,
LT170410-2WHC, LP156WF1
Reviewed-by: Robert Foss
Signed-off-by: Liu Ying
---
Marcel, I add your T-b tag from v6, let me know if you want me to drop it, as
the checkpatch fix
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