the DSC code to be guarded by the separate
> DRM_DISPLAY_DSC_HELPER Kconfig symbol.
>
> Reviewed-by: Jessica Zhang
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/amd/amdgpu/Kconfig | 1 +
> drivers/gpu/drm/display/Kconfig| 6 ++
&g
il Armstrong
> Fixes: 069a6c0e94f9 ("drm: panel: Add LG sw43408 panel driver")
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/panel/panel-lg-sw43408.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/d
n
the future, otherwise this patch is slightly unclear for anyone who isn't aware
of the current patch series and its context. Other than that, for the change
itself:
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/panel/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
>
On 2024-05-22 09:25:54, Dmitry Baryshkov wrote:
> This panel driver uses DSC PPS functions and as such depends on the
> DRM_DISPLAY_DP_HELPER. Select this symbol to make required functions
Here and in the title: maybe this is a remnant from v2, but you split out a
DRM_DISPLAY_DSC_HELPER and
On 2024-04-18 02:30:59, Dmitry Baryshkov wrote:
> On Wed, Apr 17, 2024 at 01:57:45AM +0200, Marijn Suijten wrote:
> > This comment one line down references a single, "same CTL" that controls
> > two interfaces, so the comment should clearly describe two interfaces
> >
On 2024-04-17 14:58:25, Dmitry Baryshkov wrote:
> On Wed, 17 Apr 2024 at 02:57, Marijn Suijten
> wrote:
> >
> > When configuring the timing of DSI hosts (interfaces) in
> > dsi_timing_setup() all values written to registers are taking bonded
> > DSI into account
On 2024-04-17 18:29:34, David Wronek wrote:
> Add support for the 2560x1600@90Hz OLED panel by EDO bundled with a
> Raydium RM69380 controller, as found on the Lenovo Xiaoxin Pad Pro 2021.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: David Wronek
Reviewed-by:
On 2024-04-17 11:18:58, Dmitry Baryshkov wrote:
> On Wed, 17 Apr 2024 at 02:57, Marijn Suijten
> wrote:
> >
> > Ordering issues here cause an uninitalized (default STANDALONE)
> > usecase to be programmed (which appears to be a MUX) in some cases
> > when msm
is expected to only set the slice width and
number of slices for half the panel, i.e. what will be sent by each
host individually, rather than fixing that up like hdisplay here.
Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
Signed-off-by: Marijn Suijten
---
drive
also adjusted for DSC compression) msm_host->pixel_clk_rate
which is passed to clk_set_rate() just below. Fix that by printing the
actual pixel_clk_rate that is being set.
Fixes: ed9976a09b48 ("drm/msm/dsi: adjust dsi timing for dual dsi mode")
Signed-off-by: Marijn Suijten
---
drivers/
ing into DSI0's
tree are way further down, so if this bit turns out to be a simple mux
between dsiXvco and out_div, that shouldn't have any effect as this
whole tree is off anyway.
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/dsi/dsi_manager.c | 15 +++
1 file changed,
This comment one line down references a single, "same CTL" that controls
two interfaces, so the comment should clearly describe two interfaces
used with a single active CTL and not "two CTLs".
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Ma
All other functions in dpu_hw_intf name the "self" parameter `intf`,
except dpu_hw_intf_setup_timing_engine() and the recently added
dpu_hw_intf_program_intf_cmd_cfg(). Clean that up for consistency.
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_i
w_ctl")
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index a06f69d0b257..2e50049f2f85 100644
---
ensource/display-drivers/-/blob/display-kernel.lnx.5.4.r1-rel/msm/sde/sde_encoder_phys_cmd.c?ref_type=heads#L1131-1139
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 ---
1 file changed, 3
er_phys_cmd.c?ref_type=heads#L1131-1139
Signed-off-by: Marijn Suijten
---
Marijn Suijten (7):
drm/msm/dsi: Print dual-DSI-adjusted pclk instead of original mode pclk
drm/msm/dsi: Pass bonded-DSI hdisplay/2 to DSC timing configuration
drm/msm/dpu: Always flush the slave INTF on the CTL
Hi Randy,
[..]
> Do you see differences in the generated html for these changes?
I have not yet generated the HTML locally to test this patch, but will surely do
if that's a requirement.
> " somestruct" and "" should both be OK AFAIK, although
> Documentation/doc-guide/kernel-doc.rst seems to
On 2024-04-16 20:30:49, David Wronek wrote:
> Add support for the 2560x1600@90Hz OLED panel by EDO bundled with a
> Raydium RM69380 controller, as found on the Lenovo Xiaoxin Pad Pro 2021.
>
> Signed-off-by: David Wronek
> ---
> drivers/gpu/drm/panel/Kconfig | 14 +
>
On 2024-04-15 19:50:49, Dmitry Baryshkov wrote:
> On Mon, Apr 15, 20
[...]
> > +static int rm69380_on(struct rm69380_panel *ctx)
[...]
> ret = mipi_dsi_dcs_set_display_brightness_large(dsi, 0x7ff);
Downstream may send this here, but why? As far as I've observed, update_status
also sets
also already having a `&` reference prefix in two
of the three cases. Remove the `struct` prefix to turn these references
into proper links to the designated field.
Fixes: 7beb691f1e6f ("drm: Initialize struct drm_crtc_state.no_vblank from
device settings")
Signed-off-by: Marijn Sui
On 2024-04-08 02:53:52, Dmitry Baryshkov wrote:
> Add the extended version of mipi_dsi_compression_mode(). It provides
> a way to specify the algorithm and PPS selector.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Something doesn't stick with me on the _ext() n
Can we drop (fix video mode DSC) from this patch title? It looks like more
patches are required to get this done, such a mention is more something for the
cover letter.
We could also clarify further to "set Word Count for video-mode DSC".
- Marijn
On 2024-04-03 17:10:59, Jun Nie wrote:
> From:
On 2024-04-08 17:58:29, Jun Nie wrote:
> Dmitry Baryshkov 于2024年4月3日周三 17:41写道：
> >
> > On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
> > >
> > > Add variable for slice number of a DSC compression bit stream packet.
> > > Its value shall be specified in panel driver, or default value can be set
>
On 2024-04-03 05:37:29, Dmitry Baryshkov wrote:
> On Tue, Apr 02, 2024 at 11:17:52PM +0200, Marijn Suijten wrote:
> > On 2024-04-02 02:51:15, Dmitry Baryshkov wrote:
> > > From: Sumit Semwal
> > >
> > > LG SW43408 is 1080x2160, 4-lane MIPI-DSI pan
nup and support turning off the panel]
> Signed-off-by: Caleb Connolly
> [DB: partially rewrote the driver and fixed DSC programming]
> Signed-off-by: Dmitry Baryshkov
Some small nits but I think this deserves a:
Reviewed-by: Marijn Suijten
> ---
> MAINTAINERS
On 2024-04-02 02:51:14, Dmitry Baryshkov wrote:
> Add the extended version of mipi_dsi_compression_mode(). It provides
> a way to specify the algorithm and PPS selector.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 33 +++--
>
ixes: f4dea1aaa9a1 ("drm/dsi: add helpers for DSI compression mode and PPS
> packets")
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 6 +++---
> include/drm/drm_mipi_dsi.h | 6 +++---
> 2 files changed, 6
On 2024-04-02 10:23:22, Dmitry Baryshkov wrote:
> On Tue, 2 Apr 2024 at 09:31, Krzysztof Kozlowski
> wrote:
> >
> > On 02/04/2024 01:51, Dmitry Baryshkov wrote:
> > > From: Sumit Semwal
> > >
> > > LG SW43408 is 1080x2160, 4-lane MIPI-DSI panel present on Google Pixel 3
> > > phones.
> > >
> > >
On 2024-04-01 22:11:48, Dmitry Baryshkov wrote:
> On Mon, 1 Apr 2024 at 13:29, Marijn Suijten
> wrote:
> >
> > On 2024-03-30 16:37:08, Dmitry Baryshkov wrote:
> > > On Sat, 30 Mar 2024 at 12:27, Marijn Suijten
> > > wrote:
> > > >
> &
On 2024-03-30 05:59:29, Dmitry Baryshkov wrote:
> The LG SW43408 panel requires sending non-standard data as a part of the
> MIPI_DSI_COMPRESSION_MODE packet. Rather than hacking existing
> mipi_dsi_compression_mode() add mipi_dsi_compression_mode_raw(), which
> accepts raw data buffer and length.
On 2024-03-30 16:37:08, Dmitry Baryshkov wrote:
> On Sat, 30 Mar 2024 at 12:27, Marijn Suijten
> wrote:
> >
> > On 2024-03-30 05:59:30, Dmitry Baryshkov wrote:
> > > From: Sumit Semwal
> > >
> > > LG SW43408 is 1080x2160, 4-lane MIP
On 2024-03-30 11:31:37, Marijn Suijten wrote:
> On 2024-03-30 05:53:22, Dmitry Baryshkov wrote:
> > There is little point in using %ps to print a value known to be NULL. On
> > the other hand it makes sense to print the callback symbol in the
> > 'invalid IRQ' message. Co
On 2024-03-30 05:52:29, Dmitry Baryshkov wrote:
> In case of CMD DSI panels, the vblank IRQ can be used outside of
> irq_enable/irq_disable pair. This results in the following kind of
Can you clarify when exactly that is? Is it via ops.control_vblank_irq in
dpu_encoder_toggle_vblank_for_crtc()?
ixes: 6893199183f8 ("drm/msm/dpu: stop using raw IRQ indices in the kernel
> output")
> Signed-off-by: Dmitry Baryshkov
Agreed, this is a lot more clear:
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 8
> 1 file changed
On 2024-03-30 05:59:30, Dmitry Baryshkov wrote:
> From: Sumit Semwal
>
> LG SW43408 is 1080x2160, 4-lane MIPI-DSI panel, used in some Pixel3
> phones.
>
> Whatever init sequence we have for this panel isn't capable of
> initialising it completely, toggling the reset gpio ever causes the
> panel
(), but not yet used to correctly configure
this flag.
Fixes: 58dca9810749 ("drm/msm/disp/dpu1: Add support for DSC in encoder")
Signed-off-by: Marijn Suijten
---
Note that more changes are needed to properly support the proposed 2:2:2
and 1:1:1 topology (in contrast to the already-suppo
drm_mipi_dsi.h already provides a conversion function from MIPI_DSI_FMT_
to bpp, named mipi_dsi_pixel_format_to_bpp().
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm
On 2024-01-21 20:41:05, Adam Skladowski wrote:
> Declare pinctrls for SDC pins and wire them to consumers.
>
> Signed-off-by: Adam Skladowski
Where'd the original sign-offs go?
https://lore.kernel.org/linux-arm-msm/20221214232049.703484-1-marijn.suij...@somainline.org/
Thanks taking taking
Title typo: SC8108X -> SC8180X :)
On 2023-12-03 03:32:01, Dmitry Baryshkov wrote:
> Enable WB2 hardware block, enabling writeback support on this platform.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h| 18 ++
> 1 file changed, 18
using DRM_ERROR over DPU_ERROR*, resulting
in unnecessary divergence (and un-readability) between error messages and the
code (DPU_DEBUG_CMDENC, which has a corresponding DPU_ERROR variant, is also
used within that function...)
Reviewed-by: Marijn Suijten
> drivers/gpu/drm/msm/disp/dpu1/dpu_encod
r DSI")
> Signed-off-by: Jonathan Marek
Conditional r-b assuming this will be submitted to mesa, otherwise it'll
disappear when the next person updates and regenerates these bindings.
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 +
> drivers/gpu/drm/msm/dsi
On 2023-11-14 14:00:19, Jonathan Marek wrote:
> On 11/14/23 1:28 PM, Marijn Suijten wrote:
> > On what hardware have you been testing this? Dmitry and I have a stack of
> > patches to resolve support for Active CTL programming on newer hardware (DPU
> > 5.0+ IIRC
On what hardware have you been testing this? Dmitry and I have a stack of
patches to resolve support for Active CTL programming on newer hardware (DPU
5.0+ IIRC), where a single CTL is responsible for programming multiple INTF and
DSC blocks as used in bonded DSI.
On 2023-11-14 12:42:16,
On 2023-10-09 18:36:11, Neil Armstrong wrote:
> Starting with the SM8550 platform, the SSPP & WB Clock Controls are
> no more in the MDP TOP registers, but in the SSPP & WB register space.
>
> Add the corresponding SSPP & WB ops and use them from the vbif QoS
> and OT limit setup functions.
>
>
. Set it now, splitting the vig_sblk data
> which has different version fields.
>
> Reported-by: Marijn Suijten
> Fixes: 9b6f4fedaac2 ("drm/msm/dpu: Add SM6125 support")
> Fixes: 27f0df03f3ff ("drm/msm/dpu: Add SM6375 support")
> Fixes: 3186acba5cdc ("drm/msm/dp
On 2023-08-22 10:42:07, Jessica Zhang wrote:
> DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
> 48 bits of compressed data instead of 24.
>
> Enable this mode whenever DSC is enabled for supported chipsets.
>
> Signed-off-by: Jessica Zhang
> ---
>
-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 26 +-
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 51 +++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 2 +
> 3 files changed, 46 insertions
writeback got the
> older invocation in place. This was unnoticed for several releases, but
> now it's time to fix it.
>
> Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for
> writeback")
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Ma
On 2023-08-03 22:47:24, Danila Tikhonov wrote:
> Add definitions for the display hardware used on the Qualcomm SM7150
> platform.
>
> Signed-off-by: Danila Tikhonov
> ---
> .../msm/disp/dpu1/catalog/dpu_5_2_sm7150.h| 277 ++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c|
On 2023-08-03 22:47:23, Danila Tikhonov wrote:
> Document the DPU hardware found on the Qualcomm SM7150 platform.
>
> Signed-off-by: Danila Tikhonov
> ---
> .../bindings/display/msm/qcom,sm7150-dpu.yaml | 116 ++
> 1 file changed, 116 insertions(+)
> create mode 100644
>
.
>
> Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant
> chipsets")
> Reported-by: Ryan McCann
> Reviewed-by: Abhinav Kumar
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
>
> Changes since v1:
> - Rebased o
.
>
> Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant
> chipsets")
> Reviewed-by: Abhinav Kumar
> Reviewed-by: Marijn Suijten
> Signed-off-by: Dmitry Baryshkov
> ---
>
> Changes since v1:
> - Rebased on top of the catalog
On 2023-08-02 11:08:49, Jessica Zhang wrote:
> DPU supports a data-bus widen mode for DSI INTF.
>
> Enable this mode for all supported chipsets if widebus is enabled for DSI.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ---
>
I find this title very undescriptive, it doesn't really explain from/to
where this move is happening nor why.
On 2023-08-02 11:08:48, Jessica Zhang wrote:
> Move the setting of dpu_enc.wide_bus_en to
> dpu_encoder_virt_atomic_enable() so that it mirrors the setting of
> dpu_enc.dsc.
mirroring
On 2023-07-30 03:35:18, Dmitry Baryshkov wrote:
> As the INTF is fixed at the encoder creation time, we can move the
> check whether INTF supports tearchck to dpu_encoder_phys_cmd_init().
> This function can return an error if INTF doesn't have required feature.
> Performing this check in
On 2023-07-30 03:35:12, Dmitry Baryshkov wrote:
> The DPU_PINGPONG_TE bit is set for all PINGPONG blocks on DPU < 5.0.
> Rather than checking for the flag, check for the presense of the
> corresponding interrupt line.
>
> Reviewed-by: Marijn Suijten
This patch changed s
On 2023-07-30 03:35:11, Dmitry Baryshkov wrote:
> Inline the _setup_pingpong_ops() function, it makes it easier to handle
> different conditions involving PINGPONG configuration.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> .../gpu
__field(unsigned int, irq_reg )
> + __field(unsigned int, irq_bit )
> ),
> TP_fast_assign(
> - __entry->irq_idx = irq_idx;
> + __entry->irq_reg = irq_reg;
> + __en
On 2023-07-30 01:27:06, Dmitry Baryshkov wrote:
> In preparation to reworking IRQ indcies, stop using raw indices in
IRQ indices*
> kernel output (both printk and debugfs). Instead use a pair of register
> index and bit. This corresponds closer to the values in HW catalog.
>
> Signed-off-by:
On 2023-07-30 03:22:46, Dmitry Baryshkov wrote:
> On 27/07/2023 23:12, Marijn Suijten wrote:
> > On 2023-07-27 19:21:01, Dmitry Baryshkov wrote:
> >> The DPU_INTF_TE bit is set for all INTF blocks on DPU >= 5.0, however
> >> only INTF_1 and INTF_2 actually suppor
On 2023-07-30 03:16:59, Dmitry Baryshkov wrote:
> >>> + if (!phys_enc->has_intf_te &&
> >>> + (!phys_enc->hw_pp ||
> >>> + !phys_enc->hw_pp->ops.enable_tearcheck)) {
> >>
> >> when is hw_pp assigned? Can't we also check that somewhere in an init
> >> phase?
> >
> > It would happen
On 2023-07-30 02:18:10, Dmitry Baryshkov wrote:
> On 29/07/2023 21:31, Marijn Suijten wrote:
> > On 2023-07-29 02:59:32, Dmitry Baryshkov wrote:
> >> On 27/07/2023 23:03, Marijn Suijten wrote:
> >>> On 2023-07-27 19:20:58, Dmitry Baryshkov wrote:
> >>&g
On 2023-07-29 02:31:59, Dmitry Baryshkov wrote:
> In preparation to reworking IRQ indcies, stop using raw indices in
> kernel output (both printk and debugfs). Instead use a pair of register
> index and bit. This corresponds closer to the values in HW catalog.
>
> Signed-off-by: Dmitry Baryshkov
mitry Baryshkov
Reviewed-by: Marijn Suijten
One nit all the way at the end.
> ---
> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 --
> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 4 --
> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h| 8
> .../msm/disp/dpu1/ca
Title suggestion: replace "stop using" with "Replace RAW IRQ indices in
prints with tuple" or something else that describes what the new case is
that we can expect after this PR was applied (at your discretion, it
might be hard to fit that in 72 chars). Otherwise this reads as if you
just dropped
intr_reg dpu_intr_set_7xxx[] = {
> static inline bool dpu_core_irq_is_valid(struct dpu_hw_intr *intr,
Now you can drop the intr argument :)
After fixing that:
Reviewed-by: Marijn Suijten
>int irq_idx)
> {
> - return irq_idx >= 0 &
On 2023-07-29 02:31:57, Dmitry Baryshkov wrote:
> In preparation to reworking the IRQ indices, move irq_tbl access to
> separate helper.
Nit: "to _a_ separate helper"
>
> Reviewed-by: Marijn Suijten
> Signed-off-by: Dmitry Baryshkov
> ---
> .../gpu/drm/msm/dis
ated a new helper
that now contains the validation that was open-coded before.
> Signed-off-by: Dmitry Baryshkov
For the contents though:
Reviewed-by: Marijn Suijten
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 22 +--
> 1 file changed, 11 insertions(+), 11
On 2023-07-28 18:03:35, Dmitry Baryshkov wrote:
> > > - if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
> > > + if (!irq_idx || irq_idx > intr->total_irqs) {
> > > pr_err("invalid IRQ index: [%d]\n", irq_idx);
> >
> > Logs like this might be harder to interpret (and
On 2023-07-29 02:59:32, Dmitry Baryshkov wrote:
> On 27/07/2023 23:03, Marijn Suijten wrote:
> > On 2023-07-27 19:20:58, Dmitry Baryshkov wrote:
> >> The DPU_PINGPONG_TE bit is set for all PINGPONG blocks on DPU < 5.0.
> >> Rather than checking for th
On 2023-07-29 02:45:43, Dmitry Baryshkov wrote:
> On 27/07/2023 23:10, Marijn Suijten wrote:
> > On 2023-07-27 19:21:00, Dmitry Baryshkov wrote:
> >> Inline the _setup_intf_ops() function, it makes it easier to handle
> >> different conditions involving INTF configur
On 2023-07-27 22:22:20, Marijn Suijten wrote:
> On 2023-07-27 19:21:04, Dmitry Baryshkov wrote:
> > As the INTF is fixed at the encoder creation time, we can move the
> > check whether INTF supports tearchck to dpu_encoder_phys_cmd_init().
> > This function can return an error
On 2023-07-27 23:16:22, Dmitry Baryshkov wrote:
> On 27/07/2023 23:14, Marijn Suijten wrote:
> > On 2023-07-27 19:21:02, Dmitry Baryshkov wrote:
> >> Replace the only user of the DPU_INTF_TE feature flag with the direct
> >> DPU version comparison.
> >>
On 2023-07-27 19:21:04, Dmitry Baryshkov wrote:
> As the INTF is fixed at the encoder creation time, we can move the
> check whether INTF supports tearchck to dpu_encoder_phys_cmd_init().
> This function can return an error if INTF doesn't have required feature.
> Performing this check in
ne in the vblank callback chain? I have
no clue :)
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 8
> 1 file changed, 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dp
On 2023-07-27 19:21:02, Dmitry Baryshkov wrote:
> Replace the only user of the DPU_INTF_TE feature flag with the direct
> DPU version comparison.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c |
expand "fix" to "Rather than specifying that
feature bit on DSI INTF_1 and INTF_2 exclusively..."
> corresponding interrupt line.
... which the catalog will only provide on DPU >= 5.0.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drive
On 2023-07-27 19:21:00, Dmitry Baryshkov wrote:
> Inline the _setup_intf_ops() function, it makes it easier to handle
> different conditions involving INTF configuration.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/
On 2023-07-27 19:20:59, Dmitry Baryshkov wrote:
> The DPU_PINGPONG_TE flag became unused, we can drop it now.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dp
On 2023-07-27 19:20:58, Dmitry Baryshkov wrote:
> The DPU_PINGPONG_TE bit is set for all PINGPONG blocks on DPU < 5.0.
> Rather than checking for the flag, check for the presense of the
> corresponding interrupt line.
>
> Signed-off-by: Dmitry Baryshkov
> ---
>
is more confusing to follow? Regardless of that I'm
convinced that this patch does what it's supposed to and gets rid of
some ambiguity. Maybe a comment above the IF explaining the "PP TE"
feature could alleviate the above concerns thoo. Hence:
Reviewed-by: Marijn Suijten
On 2023-07-27 22:51:32, Dmitry Baryshkov wrote:
> On 27/07/2023 22:41, Marijn Suijten wrote:
> > On 2023-07-27 22:34:59, Dmitry Baryshkov wrote:
> >> On 27/07/2023 22:29, Marijn Suijten wrote:
> >>> On 2023-07-27 18:04:54, Dmitry Baryshkov wrote:
> >>>>
Title nit: How about making this "UP by 1"?
On 2023-07-27 18:04:55, Dmitry Baryshkov wrote:
> In order to simplify IRQ declarations, shift IRQ indices by 1. This
Same here, UP by one.
> makes 0 the 'no IRQ' value. Thanks to this change, we do no longer have
> to explicitly set the 'no
On 2023-07-27 22:34:59, Dmitry Baryshkov wrote:
> On 27/07/2023 22:29, Marijn Suijten wrote:
> > On 2023-07-27 18:04:54, Dmitry Baryshkov wrote:
> >> In preparation to reworking the IRQ indices, move irq_tbl access to
> >> separate helper.
> >
> > I am
t in
a local dpu_hw_intr_entry pointer is much tidier.
Maybe I expected it to do extra mutations to irq_idx in 4/4?
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 48 +--
> .../gpu/drm/msm/disp/dpu1/
-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 3 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 2 ++
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu
On 2023-07-27 18:04:52, Dmitry Baryshkov wrote:
> There is no point in passing the IRQ index to IRQ callbacks, no function
> uses that. Drop it at last.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
On 2023-07-27 17:45:38, Dmitry Baryshkov wrote:
> Please exuse me for the spam, I missed the triggered WARN_ON because of
> the dropped patch.
>
> Declaring the mask of supported interrupts proved to be error-prone. It
> is very easy to add a bit with no corresponding backing block or to miss
>
On 2023-07-27 16:34:49, Dmitry Baryshkov wrote:
> On 27/07/2023 15:22, Dmitry Baryshkov wrote:
> >
> > On Sun, 23 Jul 2023 18:08:38 +0200, Marijn Suijten wrote:
> >> Bring up the SM6125 DPU now that all preliminary series (such as INTF
> >> TE) have been me
On 2023-07-26 10:42:24, Dmitry Baryshkov wrote:
> On 26/07/2023 10:31, Krzysztof Kozlowski wrote:
> > On 26/07/2023 09:27, Krzysztof Kozlowski wrote:
> >> On 25/07/2023 13:46, Marijn Suijten wrote:
> >>> On 2023-07-25 12:16:10, Krzysztof Kozlowski wrote:
> >>
On 2023-07-25 12:16:10, Krzysztof Kozlowski wrote:
> Example DTS should not have 'status' property.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> .../devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml | 6 --
This is not needed: it has already been corrected in v3 and v4 of the
Add the DT nodes that describe the MDSS hardware on SM6125, containing
one MDP (display controller) together with a single DSI and DSI PHY. No
DisplayPort support is added for now.
Reviewed-by: Konrad Dybcio
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Marijn Suijten
---
arch/arm64/boot/dts
Enable and configure the dispcc node on SM6125 for consumption by MDSS
later on.
Signed-off-by: Marijn Suijten
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi
b/arch/arm64/boot/dts
Enable MDSS and DSI, and configure the Samsung SOFEF01-M ams597ut01
6.0" 1080x2520 panel.
Reviewed-by: Konrad Dybcio
Signed-off-by: Marijn Suijten
---
.../dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 59 ++
1 file changed, 59 insertions(+)
diff --git a/arch/arm64
Signed-off-by: Marijn Suijten
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi
b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index cfd0901d4555..90e242ad7943 100644
--- a/arch/arm64/boot/dts/qcom/sm6125
offset
is identical to QCM2290, whose config struct can trivially be reused.
Reviewed-by: Konrad Dybcio
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
b
-domains property and a single corresponding
required-opps.
Acked-by: Krzysztof Kozlowski
Signed-off-by: Marijn Suijten
---
.../devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 11 +++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm
SM6125 has an UBWC 3.0 decoder but only an UBWC 1.0 encoder.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/msm_mdss.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index
Add definitions for the display hardware used on the Qualcomm SM6125
platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Marijn Suijten
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 236 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 7 +
drivers/gpu
Document general compatibility of the DSI controller on SM6125.
Reviewed-by: Krzysztof Kozlowski
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Marijn Suijten
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
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