The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_display.c |4 ++--
The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_display.c |4 ++--
The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_display.c |4 ++--
The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_display.c |4 ++--
The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_display.c |4 ++--
The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_display.c |4 ++--
On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> 5-9.
> Since we do all calculations based on them being register values (which are
> subtracted by 2) we need to specify them accordingly.
>
> Signed-o
On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> 5-9.
> Since we do all calculations based on them being register values (which are
> subtracted by 2) we need to specify them accordingly.
One thing I'
On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> 5-9.
> Since we do all calculations based on them being register values (which are
> subtracted by 2) we need to specify them accordingly.
>
> Signed-o
On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> 5-9.
> Since we do all calculations based on them being register values (which are
> subtracted by 2) we need to specify them accordingly.
One thing I'
On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> 5-9.
> Since we do all calculations based on them being register values (which are
> subtracted by 2) we need to specify them accordingly.
>
> Signed-o
On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> 5-9.
> Since we do all calculations based on them being register values (which are
> subtracted by 2) we need to specify them accordingly.
One thing I'
On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> 5-9.
> Since we do all calculations based on them being register values (which are
> subtracted by 2) we need to specify them accordingly.
>
> Signed-o
On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> 5-9.
> Since we do all calculations based on them being register values (which are
> subtracted by 2) we need to specify them accordingly.
One thing I'
On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> 5-9.
> Since we do all calculations based on them being register values (which are
> subtracted by 2) we need to specify them accordingly.
>
> Signed-o
On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> 5-9.
> Since we do all calculations based on them being register values (which are
> subtracted by 2) we need to specify them accordingly.
One thing I'
On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> 5-9.
> Since we do all calculations based on them being register values (which are
> subtracted by 2) we need to specify them accordingly.
>
> Signed-o
On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> 5-9.
> Since we do all calculations based on them being register values (which are
> subtracted by 2) we need to specify them accordingly.
One thing I'
On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> > 5-9.
> > Since we do all calculations based on them being register values (which are
On Fri, Feb 15, 2013 at 1:51 PM, Chris Wilson wrote:
> On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
>> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
>> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20
>> > and 5-9.
>> > Since we do all
On Fri, Feb 15, 2013 at 2:30 PM, Patrik Jakobsson
wrote:
> On Fri, Feb 15, 2013 at 1:51 PM, Chris Wilson
> wrote:
>> On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
>>> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
>>> > The Intel PRM says the M1 and M2 divisors
On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> > 5-9.
> > Since we do all calculations based on them being register values (which are
On Fri, Feb 15, 2013 at 1:51 PM, Chris Wilson wrote:
> On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
>> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
>> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20
>> > and 5-9.
>> > Since we do all
On Fri, Feb 15, 2013 at 2:30 PM, Patrik Jakobsson
wrote:
> On Fri, Feb 15, 2013 at 1:51 PM, Chris Wilson
> wrote:
>> On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
>>> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
>>> > The Intel PRM says the M1 and M2 divisors
On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> > 5-9.
> > Since we do all calculations based on them being register values (which are
On Fri, Feb 15, 2013 at 1:51 PM, Chris Wilson wrote:
> On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
>> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
>> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20
>> > and 5-9.
>> > Since we do all
On Fri, Feb 15, 2013 at 2:30 PM, Patrik Jakobsson
wrote:
> On Fri, Feb 15, 2013 at 1:51 PM, Chris Wilson
> wrote:
>> On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
>>> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
>>> > The Intel PRM says the M1 and M2 divisors
On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> > 5-9.
> > Since we do all calculations based on them being register values (which are
On Fri, Feb 15, 2013 at 1:51 PM, Chris Wilson wrote:
> On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
>> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
>> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20
>> > and 5-9.
>> > Since we do all
On Fri, Feb 15, 2013 at 2:30 PM, Patrik Jakobsson
wrote:
> On Fri, Feb 15, 2013 at 1:51 PM, Chris Wilson
> wrote:
>> On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
>>> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
>>> > The Intel PRM says the M1 and M2 divisors
On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> > 5-9.
> > Since we do all calculations based on them being register values (which are
On Fri, Feb 15, 2013 at 1:51 PM, Chris Wilson wrote:
> On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
>> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
>> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20
>> > and 5-9.
>> > Since we do all
On Fri, Feb 15, 2013 at 2:30 PM, Patrik Jakobsson
wrote:
> On Fri, Feb 15, 2013 at 1:51 PM, Chris Wilson
> wrote:
>> On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
>>> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
>>> > The Intel PRM says the M1 and M2 divisors
On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and
> > 5-9.
> > Since we do all calculations based on them being register values (which are
On Fri, Feb 15, 2013 at 1:51 PM, Chris Wilson wrote:
> On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
>> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
>> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20
>> > and 5-9.
>> > Since we do all
On Fri, Feb 15, 2013 at 2:30 PM, Patrik Jakobsson
wrote:
> On Fri, Feb 15, 2013 at 1:51 PM, Chris Wilson
> wrote:
>> On Fri, Feb 15, 2013 at 12:18:49AM +, Chris Wilson wrote:
>>> On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
>>> > The Intel PRM says the M1 and M2 divisors
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