From: Thierry Reding <tred...@nvidia.com>
Store capabilities in max_* fields and add separate fields for the
currently selected settings. This is useful to allow the current link
configuration to be stored without overwriting the capabilities.
Cc: Rob Clark <robdclark at gmail.com>
Signed-off-by: Thierry Reding <treding at nvidia.com>
---
drivers/gpu/drm/drm_dp_helper.c | 16 +++++++++++-----
drivers/gpu/drm/msm/edp/edp_ctrl.c | 8 ++++----
drivers/gpu/drm/tegra/dpaux.c | 8 ++++----
drivers/gpu/drm/tegra/sor.c | 29 ++++++++++++++---------------
include/drm/drm_dp_helper.h | 7 +++++--
5 files changed, 38 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 841b49652cc5..c00896ab8b04 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -290,9 +290,12 @@ static void drm_dp_link_reset(struct drm_dp_link *link)
return;
link->revision = 0;
- link->rate = 0;
- link->num_lanes = 0;
+ link->max_rate = 0;
+ link->max_lanes = 0;
link->capabilities = 0;
+
+ link->rate = 0;
+ link->lanes = 0;
}
/**
@@ -318,12 +321,15 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct
drm_dp_link *link)
return err;
link->revision = values[0];
- link->rate = drm_dp_bw_code_to_link_rate(values[1]);
- link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
+ link->max_rate = drm_dp_bw_code_to_link_rate(values[1]);
+ link->max_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
if (values[2] & DP_ENHANCED_FRAME_CAP)
link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
+ link->rate = link->max_rate;
+ link->lanes = link->max_lanes;
+
return 0;
}
EXPORT_SYMBOL(drm_dp_link_probe);
@@ -410,7 +416,7 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct
drm_dp_link *link)
int err;
values[0] = drm_dp_link_rate_to_bw_code(link->rate);
- values[1] = link->num_lanes;
+ values[1] = link->lanes;
if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c
b/drivers/gpu/drm/msm/edp/edp_ctrl.c
index 81200e9be382..c87a03561246 100644
--- a/drivers/gpu/drm/msm/edp/edp_ctrl.c
+++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c
@@ -416,7 +416,7 @@ static void edp_fill_link_cfg(struct edp_ctrl *ctrl)
u32 prate;
u32 lrate;
u32 bpp;
- u8 max_lane = ctrl->dp_link.num_lanes;
+ u8 max_lane = ctrl->dp_link.max_lanes;
u8 lane;
prate = ctrl->pixel_rate;
@@ -426,7 +426,7 @@ static void edp_fill_link_cfg(struct edp_ctrl *ctrl)
* By default, use the maximum link rate and minimum lane count,
* so that we can do rate down shift during link training.
*/
- ctrl->link_rate = drm_dp_link_rate_to_bw_code(ctrl->dp_link.rate);
+ ctrl->link_rate = drm_dp_link_rate_to_bw_code(ctrl->dp_link.max_rate);
prate *= bpp;
prate /= 8; /* in kByte */
@@ -714,7 +714,7 @@ static int edp_link_rate_down_shift(struct edp_ctrl *ctrl)
rate = ctrl->link_rate;
lane = ctrl->lane_cnt;
- max_lane = ctrl->dp_link.num_lanes;
+ max_lane = ctrl->dp_link.max_lanes;
bpp = ctrl->color_depth * 3;
prate = ctrl->pixel_rate;
@@ -772,7 +772,7 @@ static int edp_do_link_train(struct edp_ctrl *ctrl)
* Set the current link rate and lane cnt to panel. They may have been
* adjusted and the values are different from them in DPCD CAP
*/
- dp_link.num_lanes = ctrl->lane_cnt;
+ dp_link.lanes = ctrl->lane_cnt;
dp_link.rate = drm_dp_bw_code_to_link_rate(ctrl->link_rate);
dp_link.capabilities = ctrl->dp_link.capabilities;
if (drm_dp_link_configure(ctrl->drm_aux, &dp_link) < 0)
diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index 6aecb6647313..2c5480265ccd 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -578,14 +578,14 @@ int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct
drm_dp_link *link,
if (tp == DP_TRAINING_PATTERN_DISABLE)
return 0;
- for (i = 0; i < link->num_lanes; i++)
+ for (i = 0; i < link->lanes; i++)
values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
DP_TRAIN_PRE_EMPH_LEVEL_0 |
DP_TRAIN_MAX_SWING_REACHED |
DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values,
- link->num_lanes);
+ link->lanes);
if (err < 0)
return err;
@@ -597,13 +597,13 @@ int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct
drm_dp_link *link,
switch (tp) {
case DP_TRAINING_PATTERN_1:
- if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
+ if (!drm_dp_clock_recovery_ok(status, link->lanes))
return -EAGAIN;
break;
case DP_TRAINING_PATTERN_2:
- if (!drm_dp_channel_eq_ok(status, link->num_lanes))
+ if (!drm_dp_channel_eq_ok(status, link->lanes))
return -EAGAIN;
break;
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 3eff7cf75d25..7bf444bd1588 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -277,7 +277,7 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
if (err < 0)
return err;
- for (i = 0, value = 0; i < link->num_lanes; i++) {
+ for (i = 0, value = 0; i < link->lanes; i++) {
unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
SOR_DP_TPG_SCRAMBLER_NONE |
SOR_DP_TPG_PATTERN_TRAIN1;
@@ -298,7 +298,7 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
value |= SOR_DP_SPARE_MACRO_SOR_CLK;
tegra_sor_writel(sor, value, SOR_DP_SPARE0);
- for (i = 0, value = 0; i < link->num_lanes; i++) {
+ for (i = 0, value = 0; i < link->lanes; i++) {
unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
SOR_DP_TPG_SCRAMBLER_NONE |
SOR_DP_TPG_PATTERN_TRAIN2;
@@ -313,7 +313,7 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
if (err < 0)
return err;
- for (i = 0, value = 0; i < link->num_lanes; i++) {
+ for (i = 0, value = 0; i < link->lanes; i++) {
unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
SOR_DP_TPG_SCRAMBLER_GALIOS |
SOR_DP_TPG_PATTERN_NONE;
@@ -581,11 +581,11 @@ static int tegra_sor_calc_config(struct tegra_sor *sor,
u32 num_syms_per_line;
unsigned int i;
- if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
+ if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
return -EINVAL;
- output = link_rate * 8 * link->num_lanes;
input = pclk * config->bits_per_pixel;
+ output = link_rate * 8 * link->lanes;
if (input >= output)
return -ERANGE;
@@ -628,7 +628,7 @@ static int tegra_sor_calc_config(struct tegra_sor *sor,
watermark = div_u64(watermark + params.error, f);
config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
- (link->num_lanes * 8);
+ (link->lanes * 8);
if (config->watermark > 30) {
config->watermark = 30;
@@ -648,12 +648,12 @@ static int tegra_sor_calc_config(struct tegra_sor *sor,
if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
config->hblank_symbols -= 3;
- config->hblank_symbols -= 12 / link->num_lanes;
+ config->hblank_symbols -= 12 / link->lanes;
/* compute the number of symbols per vertical blanking interval */
num = (mode->hdisplay - 25) * link_rate;
config->vblank_symbols = div_u64(num, pclk);
- config->vblank_symbols -= 36 / link->num_lanes + 4;
+ config->vblank_symbols -= 36 / link->lanes + 4;
dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
config->vblank_symbols);
@@ -1340,17 +1340,17 @@ static void tegra_sor_edp_enable(struct drm_encoder
*encoder)
/* power DP lanes */
value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
- if (link.num_lanes <= 2)
+ if (link.lanes <= 2)
value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
else
value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
- if (link.num_lanes <= 1)
+ if (link.lanes <= 1)
value &= ~SOR_DP_PADCTL_PD_TXD_1;
else
value |= SOR_DP_PADCTL_PD_TXD_1;
- if (link.num_lanes == 0)
+ if (link.lanes == 0)
value &= ~SOR_DP_PADCTL_PD_TXD_0;
else
value |= SOR_DP_PADCTL_PD_TXD_0;
@@ -1359,7 +1359,7 @@ static void tegra_sor_edp_enable(struct drm_encoder
*encoder)
value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
- value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
+ value |= SOR_DP_LINKCTL_LANE_COUNT(link.lanes);
tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
/* start lane sequencer */
@@ -1453,7 +1453,7 @@ static void tegra_sor_edp_enable(struct drm_encoder
*encoder)
err);
rate = drm_dp_link_rate_to_bw_code(link.rate);
- lanes = link.num_lanes;
+ lanes = link.lanes;
value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
@@ -1470,8 +1470,7 @@ static void tegra_sor_edp_enable(struct drm_encoder
*encoder)
tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
/* disable training pattern generator */
-
- for (i = 0; i < link.num_lanes; i++) {
+ for (i = 0; i < link.lanes; i++) {
unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
SOR_DP_TPG_SCRAMBLER_GALIOS |
SOR_DP_TPG_PATTERN_NONE;
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index bb9d0deca07c..124fea3ffd57 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -757,9 +757,12 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
struct drm_dp_link {
unsigned char revision;
- unsigned int rate;
- unsigned int num_lanes;
+ unsigned int max_rate;
+ unsigned int max_lanes;
unsigned long capabilities;
+
+ unsigned int rate;
+ unsigned int lanes;
};
int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
--
2.5.0
