Add a check to use force DSC bpc only if it, along with the
corresponding bpp are within allowed limits.
Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index d061fc3fa402..354dbd1d3164 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1510,19 +1510,20 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
int forced_bpc = intel_dp->force_dsc_bpc;
int forced_bpp = forced_bpc * 3;
- /* Min Input BPC for ICL+ is 8 */
- if (forced_bpc < 8) {
+ if (forced_bpc < 8 || /* Min Input BPC for ICL+ is 8 */
+ forced_bpc > conn_state->max_requested_bpc ||
+ forced_bpp < limits->min_bpp ||
+ forced_bpp > limits->max_bpp) {
drm_dbg_kms(&dev_priv->drm,
- "Cannot force dsc bpc:%d, due to dsc bpc
limits\n",
+ "Cannot force dsc bpc:%d, due to bpc/bpp
limits\n",
intel_dp->force_dsc_bpc);
return -EINVAL;
}
pipe_config->pipe_bpp = forced_bpp;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n",
- pipe_config->pipe_bpp);
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n",
pipe_config->pipe_bpp);
} else if (compute_pipe_bpp) {
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
-
conn_state->max_requested_bpc);
+ int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
conn_state->max_requested_bpc);
+
if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
drm_dbg_kms(&dev_priv->drm,
"No DSC support for less than 8bpc\n");
@@ -1530,7 +1531,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
}
pipe_config->pipe_bpp = pipe_bpp;
}
-
/*
* For now enable DSC for max link rate, max lane count.
* Optimize this later for the minimum possible link rate/lane count
--
2.25.1
