[PATCH 14/17] drm/i915/guc: Ensure H2G buffer updates visible before tail update

[Matthew Brost]

Ensure H2G buffer updates are visible before descriptor tail updates by
inserting a barrier between the H2G buffer update and the tail. The
barrier is simple wmb() for SMEM and is register write for LMEM. This is
needed if more than 1 H2G can be inflight at once.

Signed-off-by: Matthew Brost <matthew.br...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index e44f06fbf87a..732a8ffa52dc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -328,6 +328,18 @@ static u32 ct_get_next_fence(struct intel_guc_ct *ct)
        return ++ct->requests.last_fence;
 }
 
+static void write_barrier(struct intel_guc_ct *ct) {
+       struct intel_guc *guc = ct_to_guc(ct);
+       struct intel_gt *gt = guc_to_gt(guc);
+
+       if (i915_gem_object_is_lmem(guc->ct.vma->obj)) {
+               GEM_BUG_ON(guc->send_regs.fw_domains);
+               intel_uncore_write_fw(gt->uncore, GEN11_SOFT_SCRATCH(0), 0);
+       } else {
+               wmb();
+       }
+}
+
 /**
  * DOC: CTB Host to GuC request
  *
@@ -411,6 +423,12 @@ static int ct_write(struct intel_guc_ct *ct,
        }
        GEM_BUG_ON(tail > size);
 
+       /*
+        * make sure H2G buffer update and LRC tail update (if this triggering a
+        * submission) are visible before updating the descriptor tail
+        */
+       write_barrier(ct);
+
        /* now update desc tail (back in bytes) */
        desc->tail = tail * 4;
        return 0;
-- 
2.28.0