Hi Guido,
On Thu, 2020-12-10 at 08:14 +0100, Guido Günther wrote:
> Hi,
> On Tue, Dec 08, 2020 at 06:03:05PM +0800, Liu Ying wrote:
> > On Tue, 2020-12-08 at 10:24 +0100, Guido Günther wrote:
> > > Hi Liu,
> > > some minor comments inline:
> > >
> > > On Fri, Dec 04, 2020 at 03:33:44PM +0800,
Hi,
On Tue, Dec 08, 2020 at 06:03:05PM +0800, Liu Ying wrote:
> On Tue, 2020-12-08 at 10:24 +0100, Guido Günther wrote:
> > Hi Liu,
> > some minor comments inline:
> >
> > On Fri, Dec 04, 2020 at 03:33:44PM +0800, Liu Ying wrote:
> > > i.MX8qxp SoC embeds a Mixel MIPI DPHY + LVDS PHY combo which
On Tue, 2020-12-08 at 10:24 +0100, Guido Günther wrote:
> Hi Liu,
> some minor comments inline:
>
> On Fri, Dec 04, 2020 at 03:33:44PM +0800, Liu Ying wrote:
> > i.MX8qxp SoC embeds a Mixel MIPI DPHY + LVDS PHY combo which supports
> > either a MIPI DSI display or a LVDS display. The PHY mode is
Hi Liu,
some minor comments inline:
On Fri, Dec 04, 2020 at 03:33:44PM +0800, Liu Ying wrote:
> i.MX8qxp SoC embeds a Mixel MIPI DPHY + LVDS PHY combo which supports
> either a MIPI DSI display or a LVDS display. The PHY mode is controlled
> by SCU firmware and the driver would call a SCU
i.MX8qxp SoC embeds a Mixel MIPI DPHY + LVDS PHY combo which supports
either a MIPI DSI display or a LVDS display. The PHY mode is controlled
by SCU firmware and the driver would call a SCU firmware function to
configure the PHY mode. The single LVDS PHY has 4 data lanes to support
a LVDS
