[PATCH 6/6] drm/amd/powerplay: add sclk OD support on Polaris10

[Alex Deucher]

From: Eric Huang <jinhuieric.hu...@amd.com>

This implements sclk overdrive(OD) overclocking support for Polaris10,
and the maximum overdrive percentage is 20.

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 4cef7a5..05cb9a0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -4899,6 +4899,48 @@ static int polaris10_get_fan_control_mode(struct 
pp_hwmgr *hwmgr)
                                CG_FDO_CTRL2, FDO_PWM_MODE);
 }

+static int polaris10_get_sclk_od(struct pp_hwmgr *hwmgr)
+{
+       struct polaris10_hwmgr *data = (struct polaris10_hwmgr 
*)(hwmgr->backend);
+       struct polaris10_single_dpm_table *sclk_table = 
&(data->dpm_table.sclk_table);
+       struct polaris10_single_dpm_table *golden_sclk_table =
+                       &(data->golden_dpm_table.sclk_table);
+       int value;
+
+       value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
+                       golden_sclk_table->dpm_levels[golden_sclk_table->count 
- 1].value) *
+                       100 /
+                       golden_sclk_table->dpm_levels[golden_sclk_table->count 
- 1].value;
+
+       return value;
+}
+
+static int polaris10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
+{
+       struct polaris10_hwmgr *data = (struct polaris10_hwmgr 
*)(hwmgr->backend);
+       struct polaris10_single_dpm_table *golden_sclk_table =
+                       &(data->golden_dpm_table.sclk_table);
+       struct pp_power_state  *ps;
+       struct polaris10_power_state  *polaris10_ps;
+
+       if (value > 20)
+               value = 20;
+
+       ps = hwmgr->request_ps;
+
+       if (ps == NULL)
+               return -EINVAL;
+
+       polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
+
+       polaris10_ps->performance_levels[polaris10_ps->performance_level_count 
- 1].engine_clock =
+                       golden_sclk_table->dpm_levels[golden_sclk_table->count 
- 1].value *
+                       value / 100 +
+                       golden_sclk_table->dpm_levels[golden_sclk_table->count 
- 1].value;
+
+       return 0;
+}
+
 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
        .backend_init = &polaris10_hwmgr_backend_init,
        .backend_fini = &polaris10_hwmgr_backend_fini,
@@ -4942,6 +4984,8 @@ static const struct pp_hwmgr_func polaris10_hwmgr_funcs = 
{
        .force_clock_level = polaris10_force_clock_level,
        .print_clock_levels = polaris10_print_clock_levels,
        .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
+       .get_sclk_od = polaris10_get_sclk_od,
+       .set_sclk_od = polaris10_set_sclk_od,
 };

 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
-- 
2.5.5