[PATCH v2 2/2] drm/bridge: add it6505 driver to read data-lanes and max-pixel-clock-khz from dt

[allen]

From: allen chen <allen.c...@ite.com.tw>

Add driver to read data-lanes and max-pixel-clock-khz from dt property to
restrict output bandwidth.

Signed-off-by: Allen chen <allen.c...@ite.com.tw>
Signed-off-by: Pin-yen Lin <treapk...@chromium.org>
---
 drivers/gpu/drm/bridge/ite-it6505.c | 35 ++++++++++++++++++++++++++---
 1 file changed, 32 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/bridge/ite-it6505.c 
b/drivers/gpu/drm/bridge/ite-it6505.c
index 2767b70fa2cb..cfa25a176a29 100644
--- a/drivers/gpu/drm/bridge/ite-it6505.c
+++ b/drivers/gpu/drm/bridge/ite-it6505.c
@@ -436,6 +436,8 @@ struct it6505 {
        bool powered;
        bool hpd_state;
        u32 afe_setting;
+       u32 max_dpi_pixel_clock;
+       u32 max_lane_count;
        enum hdcp_state hdcp_status;
        struct delayed_work hdcp_work;
        struct work_struct hdcp_wait_ksv_list;
@@ -1475,7 +1477,8 @@ static void it6505_parse_link_capabilities(struct it6505 
*it6505)
        it6505->lane_count = link->num_lanes;
        DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training",
                             it6505->lane_count);
-       it6505->lane_count = min_t(int, it6505->lane_count, MAX_LANE_COUNT);
+       it6505->lane_count = min_t(int, it6505->lane_count,
+                                  it6505->max_lane_count);
 
        it6505->branch_device = drm_dp_is_branch(it6505->dpcd);
        DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device",
@@ -2901,7 +2904,7 @@ it6505_bridge_mode_valid(struct drm_bridge *bridge,
        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
                return MODE_NO_INTERLACE;
 
-       if (mode->clock > DPI_PIXEL_CLK_MAX)
+       if (mode->clock > it6505->max_dpi_pixel_clock)
                return MODE_CLOCK_HIGH;
 
        it6505->video_info.clock = mode->clock;
@@ -3066,6 +3069,8 @@ static void it6505_parse_dt(struct it6505 *it6505)
 {
        struct device *dev = &it6505->client->dev;
        u32 *afe_setting = &it6505->afe_setting;
+       u32 *max_lane_count = &it6505->max_lane_count;
+       u32 *max_dpi_pixel_clock = &it6505->max_dpi_pixel_clock;
 
        it6505->lane_swap_disabled =
                device_property_read_bool(dev, "no-laneswap");
@@ -3081,7 +3086,31 @@ static void it6505_parse_dt(struct it6505 *it6505)
        } else {
                *afe_setting = 0;
        }
-       DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %d", *afe_setting);
+
+       if (device_property_read_u32(dev, "data-lanes",
+                                    max_lane_count) == 0) {
+               if (*max_lane_count > 4 || *max_lane_count == 3) {
+                       dev_err(dev, "max lane count error, use default");
+                       *max_lane_count = MAX_LANE_COUNT;
+               }
+       } else {
+               *max_lane_count = MAX_LANE_COUNT;
+       }
+
+       if (device_property_read_u32(dev, "max-pixel-clock-khz",
+                                    max_dpi_pixel_clock) == 0) {
+               if (*max_dpi_pixel_clock > 297000) {
+                       dev_err(dev, "max pixel clock error, use default");
+                       *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
+               }
+       } else {
+               *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
+       }
+
+       DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %u, max_lane_count: %u",
+                            it6505->afe_setting, it6505->max_lane_count);
+       DRM_DEV_DEBUG_DRIVER(dev, "using max_dpi_pixel_clock: %u kHz",
+                            it6505->max_dpi_pixel_clock);
 }
 
 static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf,
-- 
2.25.1