Am 31.03.23 um 02:06 schrieb Danilo Krummrich:
It already happend a few times that patches slipped through which
implemented access to an entity through a job that was already removed
from the entities queue. Since jobs and entities might have different
lifecycles, this can potentially cause UAF
Hello Frank,
On Thu Mar 30, 2023 at 6:45 AM CEST, Frank Oltmanns wrote:
> Roman, will you please submit a V2 of the patch I submitted then? Or do
> you want me to do it?
Yes, I'm already on it, only missing a cover letter.
Roman
https://bugzilla.kernel.org/show_bug.cgi?id=217278
The Linux kernel's regression tracker (Thorsten Leemhuis)
(regressi...@leemhuis.info) changed:
What|Removed |Added
On 3/30/2023 7:47 PM, Dmitry Baryshkov wrote:
On 31/03/2023 04:33, Abhinav Kumar wrote:
On 3/30/2023 5:16 PM, Dmitry Baryshkov wrote:
On Fri, 31 Mar 2023 at 03:07, Jessica Zhang
wrote:
On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
On
Zhao Liu wrote:
> From: Zhao Liu
>
> The use of kmap_atomic() is being deprecated in favor of
> kmap_local_page()[1], and this patch converts the calls from
> kmap_atomic() to kmap_local_page().
>
> The main difference between atomic and local mappings is that local
> mappings doesn't disable
Hi all,
Friendly ping: who can take this, please?
Thanks
--
Gustavo
On 3/17/23 12:18, Gustavo A. R. Silva wrote:
Zero-length arrays as fake flexible arrays are deprecated and we are
moving towards adopting C99 flexible-array members instead.
Address the following warning found with GCC-13
On 2023/3/30 15:26, Thomas Zimmermann wrote:
Hi
Am 30.03.23 um 09:17 schrieb Sui Jingfeng:
Hi,
On 2023/3/30 14:57, Thomas Zimmermann wrote:
Hi
Am 30.03.23 um 06:17 schrieb Lucas De Marchi:
On Wed, Mar 29, 2023 at 11:04:17AM +0200, Thomas Zimmermann wrote:
(cc'ing Lucas)
Hi
Am 25.03.23
Zhao Liu wrote:
> From: Zhao Liu
>
> The use of kmap_atomic() is being deprecated in favor of
> kmap_local_page()[1], and this patch converts the call from
> kmap_atomic() to kmap_local_page().
>
> The main difference between atomic and local mappings is that local
> mappings doesn't disable
Zhao Liu wrote:
> From: Zhao Liu
>
> The use of kmap_atomic() is being deprecated in favor of
> kmap_local_page()[1], and this patch converts the call from
> kmap_atomic() to kmap_local_page().
>
> The main difference between atomic and local mappings is that local
> mappings doesn't disable
Zhao Liu wrote:
> From: Zhao Liu
>
> The use of kmap_atomic() is being deprecated in favor of
> kmap_local_page()[1], and this patch converts the call from
> kmap_atomic() to kmap_local_page().
>
> The main difference between atomic and local mappings is that local
> mappings doesn't disable
Zhao Liu wrote:
> From: Zhao Liu
>
> The use of kmap_atomic() is being deprecated in favor of
> kmap_local_page()[1], and this patch converts the call from
> kmap_atomic() to kmap_local_page().
>
> The main difference between atomic and local mappings is that local
> mappings doesn't disable
The default hpd_wait_us in panel_edp.c is 2 seconds. This makes the
sleep time in the polling of _ps8640_wait_hpd_asserted become 200ms.
Change it to a constant 20ms to speed up the function.
Signed-off-by: Pin-yen Lin
---
drivers/gpu/drm/bridge/parade-ps8640.c | 2 +-
1 file changed, 1
On 31/03/2023 04:33, Abhinav Kumar wrote:
On 3/30/2023 5:16 PM, Dmitry Baryshkov wrote:
On Fri, 31 Mar 2023 at 03:07, Jessica Zhang
wrote:
On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On
Hi Dmitry,
Thanks for the review.
On Thu, Mar 23, 2023 at 7:39 AM Dmitry Baryshkov
wrote:
>
> On Wed, 22 Mar 2023 at 12:47, Pin-yen Lin wrote:
> >
> > Add helpers to register and unregister Type-C "switches" for bridges
> > capable of switching their output between two downstream devices.
> >
Hi Andy,
Thanks for the review.
On Wed, Mar 22, 2023 at 8:01 PM Andy Shevchenko
wrote:
>
> On Wed, Mar 22, 2023 at 06:46:32PM +0800, Pin-yen Lin wrote:
> > Add helpers to register and unregister Type-C "switches" for bridges
> > capable of switching their output between two downstream devices.
On Thu, 30 Mar 2023 08:44:34 -0700, Rodrigo Vivi wrote:
>
> On Wed, Mar 29, 2023 at 10:50:09PM -0700, Dixit, Ashutosh wrote:
> > On Tue, 28 Mar 2023 16:35:43 -0700, Ashutosh Dixit wrote:
> > >
> > > On ATSM the PL1 limit is disabled at power up. The previous uapi assumed
> > > that the PL1 limit
On ATSM the PL1 limit is disabled at power up. The previous uapi assumed
that the PL1 limit is always enabled and therefore did not have a notion of
a disabled PL1 limit. This results in erroneous PL1 limit values when the
PL1 limit is disabled. For example at power up, the disabled ATSM PL1 limit
Convert the Maxim Integrated MAX98371 audio codec bindings to DT schema.
Signed-off-by: André Morishita
---
.../devicetree/bindings/sound/max98371.txt| 17
.../bindings/sound/maxim,max98371.yaml| 41 +++
2 files changed, 41 insertions(+), 17 deletions(-)
https://bugzilla.kernel.org/show_bug.cgi?id=217278
Bug ID: 217278
Summary: ast :03:00.0: PM: DPM device timeout
during S4 resuming
Product: Drivers
Version: 2.5
Kernel Version: v6.3-rc4
Hardware: Intel
On 3/30/2023 5:16 PM, Dmitry Baryshkov wrote:
On Fri, 31 Mar 2023 at 03:07, Jessica Zhang wrote:
On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Use MSM
On 3/30/2023 6:25 PM, Dmitry Baryshkov wrote:
On 31/03/2023 04:12, Jessica Zhang wrote:
On 3/30/2023 5:16 PM, Dmitry Baryshkov wrote:
On Fri, 31 Mar 2023 at 03:07, Jessica Zhang
wrote:
On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
On
On 31/03/2023 04:12, Jessica Zhang wrote:
On 3/30/2023 5:16 PM, Dmitry Baryshkov wrote:
On Fri, 31 Mar 2023 at 03:07, Jessica Zhang
wrote:
On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On
Dear all:
Gentle ping on this patch.
Thanks
主 题：[PATCH] drm/qxl: prevent memory leak 日 期：2023-03-22 16:58 发件人：zhouzong...@kylinos.cn 收件人：airlied;Gerd Hoffmann;Dave Airlie;Daniel Vetter;
The allocated memory for qdev->dumb_heads should be releasedin qxl_destroy_monitors_object before
On 31.03.2023 03:12, Jessica Zhang wrote:
>
>
> On 3/30/2023 5:16 PM, Dmitry Baryshkov wrote:
>> On Fri, 31 Mar 2023 at 03:07, Jessica Zhang
>> wrote:
>>>
>>>
>>>
>>> On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
>
>
> On 3/29/2023
On 31.03.2023 03:14, Konrad Dybcio wrote:
> This series brings SM8[12]50 (A6[45]0) speedbin support along with a
> touch-up for 8150, allowing Adreno to cooperate with the display hw.
>
> Tested on Xperia 5 II (SM8250 Edo PDX206) and Xperia 5 (SM8150 Kumano
> Bahamut).
>
> v2 -> v3:
> - Don't
SM8250 has (at least) four GPU speed bins. With the support added on the
driver side, wire up bin detection in the DTS to restrict lower-quality
SKUs from running at frequencies they were not validated at.
Tested-by: Marijn Suijten # On Sony Xperia 5 II
(speed bin 0x7)
Reviewed-by: Marijn
Add support for matching QFPROM fuse values to get the correct speed bin
on A640 (SM8150) GPUs.
Reviewed-by: Akhil P Oommen
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git
SM8150 has (at least) two GPU speed bins. With the support added on the
driver side, wire up bin detection in the DTS to restrict lower-quality
SKUs from running at frequencies they were not validated at.
Tested-by: Marijn Suijten # On Sony Xperia 5
(speed bin 0x3)
Reviewed-by: Marijn Suijten
Add support for matching QFPROM fuse values to get the correct speed bin
on A650 (SM8250) GPUs.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 ++
1 file changed, 18 insertions(+)
diff --git
Now that there's display support, there is no reason to assume the default
mode for Adreno should be headless. Keep it like that for boards that
previously enabled it, so as not to create regressions though.
Tested-by: Marijn Suijten # On Sony Xperia 5
Reviewed-by: Marijn Suijten
Reviewed-by:
This series brings SM8[12]50 (A6[45]0) speedbin support along with a
touch-up for 8150, allowing Adreno to cooperate with the display hw.
Tested on Xperia 5 II (SM8250 Edo PDX206) and Xperia 5 (SM8150 Kumano
Bahamut).
v2 -> v3:
- Don't swap speedbin 2 (with fuse val 3) and speedbin 3 (with fuse
On 3/30/2023 5:16 PM, Dmitry Baryshkov wrote:
On Fri, 31 Mar 2023 at 03:07, Jessica Zhang wrote:
On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Use MSM
On 20/01/2023 19:22, Konrad Dybcio wrote:
Add support for matching QFPROM fuse values to get the correct speed bin
on A650 (SM8250) GPUs.
Signed-off-by: Konrad Dybcio
Reviewed-by: Dmitry Baryshkov
Thank you for the patch. It took me a while to dive into various ways
vendor kernels handle
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by Media tile update the whole
cache line even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to different locations within a single cache line.
From: Fei Yang
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with addition of support for ADM/L4 cache calls a
MOCS/PAT table update.
Also add PTE encode functions for MTL as it has different PAT
index definition than previous platforms.
BSpec: 44509, 45101, 44235
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
On Fri, 31 Mar 2023 at 03:07, Jessica Zhang wrote:
>
>
>
> On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
> > On 31/03/2023 01:49, Jessica Zhang wrote:
> >>
> >>
> >> On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
> >>> On 30/03/2023 02:18, Jessica Zhang wrote:
> Use MSM and DRM DSC helper
On 3/30/23 18:19, Lucas Stach wrote:
Hi Dave, Daniel,
please pull the following fixes for the next rc. One fix to get rid of
a memory leak showing up in the wild and two reverts to get rid of the
scheduler use-after-free reported by Danilo.
Besides the reverts, we might want to consider
clang with W=1 reports
drivers/gpu/drm/amd/amdgpu/../display/modules/freesync/freesync.c:1132:15:
error: variable
'average_render_time_in_us' set but not used
[-Werror,-Wunused-but-set-variable]
unsigned int average_render_time_in_us = 0;
^
This variable is not
Hi Jonathan,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-exynos/exynos-drm-next drm-intel/for-linux-next
drm-tip/drm-tip next-20230330]
[cannot apply to drm-misc/drm-misc-next drm-intel/for-linux-next-fixes
On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Use MSM and DRM DSC helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18
It already happend a few times that patches slipped through which
implemented access to an entity through a job that was already removed
from the entities queue. Since jobs and entities might have different
lifecycles, this can potentially cause UAF bugs.
In order to make it obvious that a jobs
clang with W=1 reports
drivers/gpu/drm/amd/amdgpu/../display/modules/freesync/freesync.c:1132:15:
error: variable
'average_render_time_in_us' set but not used
[-Werror,-Wunused-but-set-variable]
unsigned int average_render_time_in_us = 0;
^
This variable is not
A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It
features no GMU, as it's implemented solely on SoCs with SMD_RPM.
What's more interesting is that it does not feature a VDDGX line
either, being powered solely by VDDCX and has an unfortunate hardware
quirk that makes its reset
Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also
need REG_A6XX_GBIF_HALT to be set to 0. For GMU-equipped GPUs this is
done in a6xx_bus_clear_pending_transactions(), but for the GMU-less
ones we have to do it *somewhere*. Unhalting both side by side sounds
like a good plan and
Before transitioning to using per-SoC and not per-Adreno speedbin
fuse values (need another patchset to land elsewhere), a good
improvement/stopgap solution is to use adreno_is_aXYZ macros in
place of explicit revision matching. Do so to allow differentiating
between A619 and A619_holi.
A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375
(blair). This is what seems to be a first occurrence of this happening,
but it's easy to overcome by guarding the SoC-specific fuse values with
of_machine_is_compatible(). Do just that to enable frequency limiting
on these
Adreno 619 expects some tunables to be set differently. Make up for it.
Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff
A610 and A619_holi don't support the feature. Disable it to make the GPU stop
crashing after almost each and every submission - the received data on
the GPU end was simply incomplete in garbled, resulting in almost nothing
being executed properly. Extend the disablement to adreno_has_gmu_wrapper,
The GPU can only be one at a time. Turn a series of ifs into if +
elseifs to save some CPU cycles.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
but don't implement the associated GMUs. This is due to the fact that
the GMU directly pokes at RPMh. Sadly, this means we have to take care
of enabling & scaling power rails, clocks and bandwidth ourselves.
Reuse existing
A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
(trinket) and SM6225 (khaje). Trinket does not support speed binning
(only a single SKU exists) and we don't yet support khaje upstream.
Hence, add a fuse mapping table for bengal to allow for per-chip
frequency limiting.
A619_holi is a GMU-less variant of the already-supported A619 GPU.
It's present on at least SM4350 (holi) and SM6375 (blair). No mesa
changes are required. Add the required kernel-side support for it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 47
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat
Rename lower_bit to hbb_lo and explain what it signifies.
Add explanations (wherever possible to other tunables).
Port setting min_access_length, ubwc_mode and hbb_hi from downstream.
Reviewed-by: Rob Clark
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 39
These two will be reused by at least A619_holi in the non-gmu
paths. Turn them non-static them to make it possible.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++
2 files changed, 4
Recently I contributed the switch to OPP API for all Adreno generations.
I did however also skip over the fact that GPUs with a GMU don't specify
a core clock of any kind in the GPU node. While that didn't break
anything, it did introduce unwanted spam in the dmesg:
adreno 500.gpu: error
v4 -> v5:
- Add a newline before the new allOf:if: [3/15]
- Enforce 6 clocks on A619_holi/A610 [2/15]
- Pick up tags
- Improve error handling in a6xx_pm_resume [6/15]
- Add patch [1/15] (fix an existing issue) which can be picked
separately and account for it in [6/15]
- Rebase atop Akhil's CX
The adreno_load_gpu() path is guarded by an error check on
adreno_load_fw(). This function is responsible for loading
Qualcomm-only-signed binaries (e.g. SQE and GMU FW for A6XX), but it
does not take the vendor-signed ZAP blob into account.
By embedding the SQE (and GMU, if necessary) firmware
On 31/03/2023 01:49, Jessica Zhang wrote:
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Use MSM and DRM DSC helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
1 file changed, 12
On 3/29/2023 5:40 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/Makefile | 1 +
Zhao Liu wrote:
> From: Zhao Liu
>
> The use of kmap_atomic() is being deprecated in favor of
> kmap_local_page()[1], and this patch converts the call from
> kmap_atomic() + memcpy() to memcpy_[from/to]_page(), which use
> kmap_local_page() to build local mapping and then do memcpy().
>
> The
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Use MSM and DRM DSC helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git
On Thu, 2023-03-30 at 20:13 +0200, Matthieu Baerts wrote:
> As a follow-up of a previous patch modifying the documentation to
> allow using the "Closes:" tag, checkpatch.pl is updated accordingly.
>
> checkpatch.pl now no longer complain when the "Closes:" tag is used by
> itself or after the
On 30.03.2023 23:53, Dmitry Baryshkov wrote:
> Enable DSPP blocks on sc8180x platform, basing on the vendor dtsi.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 ++
> 1 file changed, 2 insertions(+)
On 30.03.2023 23:53, Dmitry Baryshkov wrote:
> Theoretically since sm8150 we should be using a single CTL for the
> source split case, but since we do not support it for now, fallback to
> DPU_CTL_SPLIT_DISPLAY.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
>
On 30.03.2023 23:53, Dmitry Baryshkov wrote:
> For sm8150+ the DPU_CTL_SPLIT_DISPLAY should be replaced with
> DPU_CTL_ACTIVE_CFG support (which supports having a single CTL for both
> interfaces in a split). Add comments where this conversion is required.
>
> Signed-off-by: Dmitry Baryshkov
This allows us to advertise more modes especially on HDR displays.
Fixes using 4K@60 modes on my TV and main display both using a HDMI to DP
adapter. Also fixes similiar issues for users running into this.
Cc: sta...@vger.kernel.org # 5.10+
Signed-off-by: Karol Herbst
---
On Thu, 30 Mar 2023 21:53:03 + David Laight wrote:
> > But wouldn't all these issues be addressed by simply doing
> >
> > #define is_power_of_2(n) (n != 0 && ((n & (n - 1)) == 0))
> >
> > ?
> >
> > (With suitable tweaks to avoid evaluating `n' more than once)
>
> I think you need to use
From: Andrew Morton
> Sent: 30 March 2023 20:51
>
> On Thu, 30 Mar 2023 13:42:39 +0300 Jani Nikula wrote:
>
> > is_power_of_2() only works for types <= sizeof(unsigned long) and it's
> > also not a constant expression. There are a number of places in kernel
> > where is_power_of_2() is called
Zhao Liu wrote:
> From: Zhao Liu
>
> The use of kmap_atomic() is being deprecated in favor of
> kmap_local_page()[1], and this patch converts the call from
> kmap_atomic() to kmap_local_page().
>
> The main difference between atomic and local mappings is that local
> mappings doesn't disable
To ease review and reuse rename VIG and DMA feature masks to contain
base DPU version since which this mask is used.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 16 +++
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 16
Remove duplicate between sc8280xp and sm8450, which belong to the same
DPU major revision.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 107 ++---
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h| 112
Drop the version comparison macros from dpu_hw_catalog.h, they are
unused.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 16
1 file changed, 16 deletions(-)
diff --git
To ease review and reuse rename MIXER feature masks to contain base DPU
version since which this mask is used.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 12 ++--
Remove duplicate between sm6115 and qcm2290, which belong to the same
DPU major revision.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h| 36 --
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 66 ---
To ease review and reuse rename INTF feature masks to contain base DPU
version since which this mask is used.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h| 8
.../drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 8
To ease review and reuse rename MERGE_3D feature masks to contain base
DPU version since which this mask is used.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Use defined name DEFAULT_DPU_OUTPUT_LINE_WIDTH instead of open coding
the value.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Duplicate some of sm8350 catalog entries to remove dependencies between
DPU major generations.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git
Duplicate some of sm8150 catalog entries to remove dependencies between
DPU major generations.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h| 134 --
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h| 34 -
After fixing scaler version we are sure that sm8450 and sc8280xp vig
sblk's are duplicates of sm8250_vig_sblk and thus can be dropped.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 8
Enable DSPP blocks on sc8180x platform, basing on the vendor dtsi.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
IRQ masks are rarely shared between different DPU revisions. Inline them
to the dpu_mdss_cfg intances and drop them from the dpu_hw_catalog.c
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 9 ++-
For sm8150+ the DPU_CTL_SPLIT_DISPLAY should be replaced with
DPU_CTL_ACTIVE_CFG support (which supports having a single CTL for both
interfaces in a split). Add comments where this conversion is required.
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 188 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 190 +-
2 files changed, 190 insertions(+), 188 deletions(-)
create mode 100644
To ease review and reuse rename CTL feature masks to contain base DPU
version since which this mask is used.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 10 +-
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 10
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h| 193 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 186 +
2 files changed, 194 insertions(+), 185 deletions(-)
create mode 100644
Remove duplicate between sc8180x and sm8150, which belong to the same
DPU major revision. The merged file is named using the DPU major version
and the amount of LM units.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h| 172
Theoretically since sm8150 we should be using a single CTL for the
source split case, but since we do not support it for now, fallback to
DPU_CTL_SPLIT_DISPLAY.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 5 +++--
1 file changed, 3
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h| 147 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 143 +
2 files changed, 148 insertions(+), 142 deletions(-)
create mode 100644
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h| 95 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 89 +
2 files changed, 97 insertions(+), 87 deletions(-)
create mode 100644
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h| 130 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 131 +-
2 files changed, 131 insertions(+), 130 deletions(-)
create mode 100644
Mark DSPP_2 and DSPP_3 as used for LM_2 and LM_3
Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Duplicate some of sc7180 catalog entries to remove dependencies between
DPU major generations.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 115 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 107 +---
2 files changed, 116 insertions(+), 106 deletions(-)
create mode 100644
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 194 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 188 +
2 files changed, 195 insertions(+), 187 deletions(-)
create mode 100644
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 107 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 105 +
2 files changed, 108 insertions(+), 104 deletions(-)
create mode 100644
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 202 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 207 +-
2 files changed, 203 insertions(+), 206 deletions(-)
create mode 100644
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