1x_client_register(&sor->client);
> + if (err < 0) {
> + dev_err(&pdev->dev, "failed to register host1x client: %d\n",
> + err);
> + goto uninit;
> }
>
> return 0;
>
> -u
On 13/02/2021 10:15, Mikko Perttunen wrote:
> Add support for booting and using NVDEC on Tegra210, Tegra186
> and Tegra194 to the Host1x and TegraDRM drivers. Booting in
> secure mode is not currently supported.
>
> Signed-off-by: Mikko Perttunen
> ---
> drivers/gpu/drm/tegra/Makefile | 3 +-
Hi Dmitry,
On 23/11/2020 00:27, Dmitry Osipenko wrote:
> Add EMC OPP DVFS tables and update board device-trees by removing
> unsupported OPPs.
>
> Signed-off-by: Dmitry Osipenko
This change is generating the following warning on Tegra20 Ventana
and prevents the EMC from probing ...
[2.48571
On 30/11/2020 22:57, Dmitry Osipenko wrote:
> 01.12.2020 00:17, Jon Hunter пишет:
>> Hi Dmitry,
>>
>> On 23/11/2020 00:27, Dmitry Osipenko wrote:
>>> Add EMC OPP DVFS tables and update board device-trees by removing
>>> unsupported OPPs.
>>>
>&
using older versions of GCC.
Fix this by using the '##__VA_ARGS__' macro instead.
Fixes: 43636451db8c ("drm/tegra: Implement job submission part of new UAPI")
Reported-by: Linux Kernel Functional Testing
Signed-off-by: Jon Hunter
---
drivers/gpu/drm/tegra/submit.c | 2 +-
Deferred probe is an expected return value for tegra_output_probe().
Given that the driver deals with it properly, there's no need to output
a warning that may potentially confuse users.
Signed-off-by: Jon Hunter
---
drivers/gpu/drm/tegra/sor.c | 2 +-
1 file changed, 1 insertion(+), 1 del
On 03/11/2020 11:44, Jon Hunter wrote:
> Deferred probe is an expected return value for tegra_output_probe().
> Given that the driver deals with it properly, there's no need to output
> a warning that may potentially confuse users.
>
> Signed-off-by: Jon Hunter
> ---
&
Deferred probe is an expected return value for tegra_output_probe().
Given that the driver deals with it properly, there's no need to output
a warning that may potentially confuse users.
Signed-off-by: Jon Hunter
---
Changes since V1:
- This time, I actually validated it!
drivers/gp
On 04/11/2020 10:49, Dmitry Osipenko wrote:
> 04.11.2020 12:23, Jon Hunter пишет:
>> Deferred probe is an expected return value for tegra_output_probe().
>> Given that the driver deals with it properly, there's no need to output
>> a warning that may potentially confuse
Deferred probe is an expected return value for tegra_output_probe().
Given that the driver deals with it properly, there's no need to output
a warning that may potentially confuse users.
Signed-off-by: Jon Hunter
---
Changes since V2:
- Removed duplicate errno print
Changes since V1:
- This
On 29/03/2022 11:37, cgel@gmail.com wrote:
From: Lv Ruyi
Before leave the nvdec_load_firmware, we shuold free virt which is alloced
s/shuold/should
s/alloced/allocated
by dma_alloc_coherent, so change "return err" to "goto cleanup".
Reported-by: Zeal Robot
Signed-off-by: Lv Ruyi
--
have not been used yet. Note that when the syncpt status
is dumped by the kernel itself for debugging only the active syncpt are
shown.
Signed-off-by: Jon Hunter
---
drivers/gpu/host1x/debug.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/host1x
Will, Joerg, Rob,
On 08/11/2021 10:36, Mikko Perttunen wrote:
On 9/16/21 5:32 PM, Mikko Perttunen wrote:
Hi all,
***
New in v2:
Added support for Tegra194
Use standard iommu-map property instead of custom mechanism
***
this series adds support for Host1x 'context isolation'. Since
when progr
Hi all,
Still no response on this :-(
On 06/12/2021 09:55, Jon Hunter wrote:
Will, Joerg, Rob,
On 08/11/2021 10:36, Mikko Perttunen wrote:
On 9/16/21 5:32 PM, Mikko Perttunen wrote:
Hi all,
***
New in v2:
Added support for Tegra194
Use standard iommu-map property instead of custom
On 14/12/2021 15:38, Robin Murphy wrote:
...
IOMMU/DT folks, any thoughts about this approach? The patches that are
of interest outside of Host1x/TegraDRM specifics are patches 1, 2, 4,
and 5.
FWIW it looks fairly innocuous to me. I don't understand host1x -
neither hardware nor driver ab
Hi Dmitry, Thierry,
On 30/11/2021 23:23, Dmitry Osipenko wrote:
Add runtime PM and OPP support to the Host1x driver. For the starter we
will keep host1x always-on because dynamic power management require a major
refactoring of the driver code since lot's of code paths are missing the
RPM handlin
On 21/12/2021 20:58, Dmitry Osipenko wrote:
Hi,
Thank you for testing it all.
21.12.2021 21:55, Jon Hunter пишет:
Hi Dmitry, Thierry,
On 30/11/2021 23:23, Dmitry Osipenko wrote:
Add runtime PM and OPP support to the Host1x driver. For the starter we
will keep host1x always-on because
On 22/12/2021 09:47, Jon Hunter wrote:
On 21/12/2021 20:58, Dmitry Osipenko wrote:
Hi,
Thank you for testing it all.
21.12.2021 21:55, Jon Hunter пишет:
Hi Dmitry, Thierry,
On 30/11/2021 23:23, Dmitry Osipenko wrote:
Add runtime PM and OPP support to the Host1x driver. For the starter
On 22/12/2021 19:01, Dmitry Osipenko wrote:
...
diff --git a/drivers/gpu/host1x/syncpt.c b/drivers/gpu/host1x/syncpt.c
index e08e331e46ae..8194826c9ce3 100644
--- a/drivers/gpu/host1x/syncpt.c
+++ b/drivers/gpu/host1x/syncpt.c
@@ -137,6 +137,15 @@ void host1x_syncpt_restore(struct host1x *hos
On 02/08/16 07:26, Tomeu Vizoso wrote:
> On 23 June 2016 at 17:59, Jon Hunter wrote:
>> If the 'i2c-bus' device-tree node is present for an I2C adapter then
>> parse this subnode for I2C slaves.
>>
>> Signed-off-by: Jon Hunter
>> ---
>> drivers/
ERR(dpaux->pinctrl)) {
> dev_err(&pdev->dev, "failed to register pincontrol\n");
> - return -ENODEV;
> + return PTR_ERR(dpaux->pinctrl);
> }
> #endif
> /* enable and clear all interrupts */
>
Acked-by: Jon Hunter
Cheers!
Jon
--
nvpublic
t it first and then find a safer solution instead.
>
> Reported-by: Tony Lindgren
> Signed-off-by: Nicolin Chen
> ---
> Tony,
>
> Would you please test and verify? Thanks!
This also fixes various memory allocation failures we have seen on
32-bit Tegra as well.
T
On 18/06/2019 16:19, Greg Kroah-Hartman wrote:
> On Fri, Jun 14, 2019 at 10:36:14PM +0200, Daniel Vetter wrote:
>> Greg is busy already, but maybe he won't do everything ...
>>
>> Cc: Greg Kroah-Hartman
>> Signed-off-by: Daniel Vetter
>> ---
>> Documentation/gpu/todo.rst | 3 +++
>> 1 file chan
On 09/07/2019 13:52, Dmitry Osipenko wrote:
> 09.07.2019 15:45, Maxime Ripard пишет:
>> Hi,
>>
>> On Fri, Jul 05, 2019 at 07:54:47PM +0300, Dmitry Osipenko wrote:
>>> 17.06.2019 17:51, Maxime Ripard пишет:
From: Maxime Ripard
Rewrite the command line parser in order to get away fro
On 09/07/2019 14:26, Jon Hunter wrote:
>
> On 09/07/2019 13:52, Dmitry Osipenko wrote:
>> 09.07.2019 15:45, Maxime Ripard пишет:
>>> Hi,
>>>
>>> On Fri, Jul 05, 2019 at 07:54:47PM +0300, Dmitry Osipenko wrote:
>>>> 17.06.2019 17
t;hpd_gpio)) {
> + if (PTR_ERR(output->hpd_gpio) == -ENOENT)
> + output->hpd_gpio = NULL;
> + else
> + return PTR_ERR(output->hpd_gpio);
> + }
>
> if (output->hpd_gpio) {
> err = gpiod_to_irq(output->hpd_gpio);
>
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 24/07/2019 10:27, Dmitry Osipenko wrote:
> 23.07.2019 15:40, Viswanath L пишет:
>> HDMI plugout calls runtime suspend, which clears interrupt registers
>> and causes audio functionality to break on subsequent plug-in; setting
>> interrupt registers in sor_audio_prepare() solves the issue.
>>
>
Hi Uwe,
On 14/03/2022 14:16, Uwe Kleine-König wrote:
Allow to add an exit hook to devm managed clocks. Also use
clk_get_optional() in devm_clk_get_optional instead of open coding it.
The generalisation will be used in the next commit to add some more
devm_clk helpers.
Reviewed-by: Jonathan Came
On 21/06/2022 21:49, Uwe Kleine-König wrote:
On Tue, Jun 21, 2022 at 08:57:00PM +0100, Jon Hunter wrote:
Some of our Tegra boards are not booting with the current -next and
bisect is pointing to this commit. Looking at the boot log I am
seeing the following panic ...
[2.097048] 8
Sparse warns about the following cast in the function
falcon_copy_firmware_image() ...
drivers/gpu/drm/tegra/falcon.c:66:27: warning: cast to restricted __le32
Fix this by casting the firmware data array to __le32 instead of u32.
Signed-off-by: Jon Hunter
---
drivers/gpu/drm/tegra/falcon.c
accelerator."
Hi,
nice to see this work going on. For subsequent revisions, can you please
also Cc the Tegra mailing list (linux-te...@vger.kernel.org) as well as
the Tegra platform maintainers (that's Jon Hunter and myself). This will
make sure that more people with an interest in thi
t the need to explicitly remove the
final reference to the mapping in the cache.
Signed-off-by: Thierry Reding
I have tested this and verified that it is working well.
Reviewed-by: Jon Hunter
Tested-by: Jon Hunter
Thanks
Jon
--
nvpublic
el0_sync_handler+0xf4/0x1b0
el0_sync+0x140/0x180
Fix this by ensuring that the regulators are disabled, if enabled, on
probe failure.
Finally, ensure that the vddio regulator is disabled in the driver
remove handler.
Signed-off-by: Jon Hunter
---
drivers/video/backlight/lp855x_bl.c | 20
Hi Lee, Daniel,
On 24/02/2020 14:37, Daniel Thompson wrote:
> On Mon, Feb 24, 2020 at 02:07:48PM +0000, Jon Hunter wrote:
>> If probing the LP885x backlight fails after the regulators have been
>> enabled, then the following warning is seen when releasing the
>> regulators ..
On 10/06/2021 12:04, Mikko Perttunen wrote:
> Implement the job submission IOCTL with a minimum feature set.
>
> Signed-off-by: Mikko Perttunen
> ---
> v7:
> * Allocate gather BO with DMA API to get page-aligned
> memory
> * Add error prints to a few places where they were missing
> v6:
> * R
Hi Mikko,
On 10/06/2021 12:04, Mikko Perttunen wrote:
> Implement the job submission IOCTL with a minimum feature set.
>
> Signed-off-by: Mikko Perttunen
> ---
> v7:
> * Allocate gather BO with DMA API to get page-aligned
> memory
> * Add error prints to a few places where they were missing
>
t. As of commit 57365a04c921 ("iommu: Move bus setup to
IOMMU device registration") that bodge no longer works, but really the
GPU driver should be responsible for its own behaviour anyway. Make the
workaround explicit.
Reported-by: Jon Hunter
Suggested-by: Dmitry Osipenko
Signed-off-by: Ro
it 57365a04c921 ("iommu: Move bus setup to
IOMMU device registration") that bodge no longer works, but really the
GPU driver should be responsible for its own behaviour anyway. Make the
workaround explicit.
Reported-by: Jon Hunter
Suggested-by: Dmitry Osipenko
Signed-off-by: Robin M
Hi Thierry, Krzysztof,
On 24/10/2022 14:15, Thierry Reding wrote:
On Tue, Sep 20, 2022 at 11:11:56AM +0300, Mikko Perttunen wrote:
From: Mikko Perttunen
On Tegra234 NVDEC firmware is loaded from a secure carveout, where it
has been loaded by a bootloader. When booting NVDEC, we need to tell i
On 04/11/2022 15:35, Krzysztof Kozlowski wrote:
On 04/11/2022 11:33, Jon Hunter wrote:
Hi Thierry, Krzysztof,
On 24/10/2022 14:15, Thierry Reding wrote:
On Tue, Sep 20, 2022 at 11:11:56AM +0300, Mikko Perttunen wrote:
From: Mikko Perttunen
On Tegra234 NVDEC firmware is loaded from a
On 04/11/2022 15:48, Krzysztof Kozlowski wrote:
On 04/11/2022 11:46, Jon Hunter wrote:
On 04/11/2022 15:35, Krzysztof Kozlowski wrote:
On 04/11/2022 11:33, Jon Hunter wrote:
Hi Thierry, Krzysztof,
On 24/10/2022 14:15, Thierry Reding wrote:
On Tue, Sep 20, 2022 at 11:11:56AM +0300, Mikko
Thierry,
On 21/10/2022 08:41, Jon Hunter wrote:
On 20/10/2022 15:23, Robin Murphy wrote:
Since commit c7e3ca515e78 ("iommu/tegra: gart: Do not register with
bus") quite some time ago, the GART driver has effectively disabled
itself to avoid issues with the GPU driver expecting it
On 08/03/2023 16:56, Nathan Chancellor wrote:
Ping? This warning is now in 6.3-rc1.
Thierry is away at the moment.
David, Daniel, do you want to pick this up directly in the meantime as a
fix for 6.3? Mikko has already reviewed and FWIW ...
Reviewed-by: Jon Hunter
Thanks
Jon
On Thu
Hi Tomeu,
On 09/09/16 10:56, Tomeu Vizoso wrote:
> Adds files and directories to debugfs for controlling and reading frame
> CRCs, per CRTC:
>
> dri/0/crtc-0/crc
> dri/0/crtc-0/crc/control
> dri/0/crtc-0/crc/data
>
> Drivers can implement the set_crc_source callback() in drm_crtc_funcs to
> star
On 04/10/16 12:25, Daniel Vetter wrote:
> On Tue, Oct 4, 2016 at 12:10 PM, Jon Hunter wrote:
>> Looks like crtc is a errno in the above case. I see this function is
>> called by looping through all the crtc and we never check to see if
>> they are valid. Should we?
>
&g
On 16/04/17 05:08, Wei Yongjun wrote:
> From: Wei Yongjun
>
> PTR_ERR should access the value just tested by IS_ERR, otherwise
> the wrong error code will be returned.
>
> Fixes: b386c6b73ac6 ("gpu: host1x: Support module reset")
> Signed-off-by: Wei Yongjun
> ---
> drivers/gpu/host1x/dev.c |
On 07/07/17 07:11, Gustavo A. R. Silva wrote:
> Check return value from call to of_match_device()
> in order to prevent a NULL pointer dereference.
>
> In case of NULL print error message and return.
>
> Signed-off-by: Gustavo A. R. Silva
> ---
> drivers/gpu/drm/tegra/sor.c | 4
> 1 file
er pincontrol\n");
> - return -ENODEV;
> + return PTR_ERR(dpaux->pinctrl);
> }
> #endif
> /* enable and clear all interrupts */
Thanks for the fix!
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 04/05/16 12:39, Laxman Dewangan wrote:
> The function tegra_pmc_readl() returns the u32 type data and hence
> change the data type of variable where this data is stored to u32
> type.
>
> Signed-off-by: Laxman Dewangan
>
> ---
> Changes from V1:
> -This is new in series as per discussion on
On 04/05/16 12:39, Laxman Dewangan wrote:
> The IO pins of Tegra SoCs are grouped for common control of IO
> interface like setting voltage signal levels and power state of
> the interface. The group is generally referred as IO pads. The
> power state and voltage control of IO pins can be done at
On 04/05/16 12:39, Laxman Dewangan wrote:
> Power Management Controller(PMC) of Tegra does the multiple chip
> power related functionality for internal and IO interfacing.
> Some of the functionalities are power gating of IP blocks, IO pads
> voltage and power state configuration, system power sta
On 05/05/16 10:52, Laxman Dewangan wrote:
>
> On Thursday 05 May 2016 03:19 PM, Jon Hunter wrote:
>> On 04/05/16 12:39, Laxman Dewangan wrote:
>>> The function tegra_pmc_readl() returns the u32 type data and hence
>>> change the data type of variable where this
On 05/05/16 13:35, Laxman Dewangan wrote:
>
> On Thursday 05 May 2016 06:13 PM, Jon Hunter wrote:
>> On 05/05/16 10:52, Laxman Dewangan wrote:
>>> On Thursday 05 May 2016 03:19 PM, Jon Hunter wrote:
>>>> On 04/05/16 12:39, Laxman Dewangan wrote:
>>>>
On 05/05/16 11:32, Laxman Dewangan wrote:
>
> On Thursday 05 May 2016 03:43 PM, Jon Hunter wrote:
>> On 04/05/16 12:39, Laxman Dewangan wrote:
>
>> +return -EINVAL;
>> +
>> +for (i = 0; i < soc->num_io_pads; ++i) {
>> +
On 05/05/16 14:09, Laxman Dewangan wrote:
>
> On Thursday 05 May 2016 06:38 PM, Jon Hunter wrote:
>> On 05/05/16 11:32, Laxman Dewangan wrote:
>>> On Thursday 05 May 2016 03:43 PM, Jon Hunter wrote:
>>>> On 04/05/16 12:39, Laxman Dewangan wrote:
>>>>
On 05/05/16 14:35, Laxman Dewangan wrote:
>
> On Thursday 05 May 2016 07:03 PM, Jon Hunter wrote:
>> On 05/05/16 14:09, Laxman Dewangan wrote:
>>> On Thursday 05 May 2016 06:38 PM, Jon Hunter wrote:
>>>> On 05/05/16 11:32, Laxman Dewangan wrote:
>>>>&
lt; 30)
> +#define IO_DPD_REQ_CODE_MASK (3U << 30)
>
> #define IO_DPD_STATUS0x1bc
> #define IO_DPD2_REQ 0x1c0
> @@ -96,10 +96,10 @@
> #define PMC_SCRATCH54_ADDR_SHIFT 0
>
> #define PMC_SCRATCH55
gt;powergates_lock);
> @@ -935,8 +936,9 @@ EXPORT_SYMBOL(tegra_io_rail_power_on);
>
> int tegra_io_rail_power_off(unsigned int id)
> {
> - unsigned long request, status, value;
> - unsigned int bit, mask;
> + unsigned long request, status;
> + unsigned int bit;
> + u32 value, mask;
> int err;
>
> mutex_lock(&pmc->powergates_lock);
>
Reviewed-by: Jon Hunter
Cheers
Jon
On 06/05/16 11:45, Laxman Dewangan wrote:
> The IO pins of Tegra SoCs are grouped for common control of IO
> interface like setting voltage signal levels and power state of
> the interface. The group is generally referred as IO pads. The
> power state and voltage control of IO pins can be done at
On 06/05/16 16:32, Laxman Dewangan wrote:
>
> On Friday 06 May 2016 08:07 PM, Jon Hunter wrote:
>> On 06/05/16 11:45, Laxman Dewangan wrote:
>> +
>> +/* Last entry */
>> +TEGRA_IO_PAD_MAX,
>> Nit should these be TEGRA_IO_PADS_xxx?
>
> Because th
On 11/05/16 14:28, Laxman Dewangan wrote:
> On Sunday 08 May 2016 05:43 PM, Jon Hunter wrote:
>> On 06/05/16 16:32, Laxman Dewangan wrote:
>>> On Friday 06 May 2016 08:07 PM, Jon Hunter wrote:
>>>> On 06/05/16 11:45, Laxman Dewangan wrote:
On 11/05/16 18:22, Laxman Dewangan wrote:
>
> On Wednesday 11 May 2016 09:05 PM, Jon Hunter wrote:
>> On 11/05/16 14:28, Laxman Dewangan wrote:
>>> On Sunday 08 May 2016 05:43 PM, Jon Hunter wrote:
>>>> On 06/05/16 16:32, Laxman Dewangan wrote:
>>>>
r.
Finally, add a warning if allocating memory for the state information
fails in tegra_dsi_connector_reset().
Fixes: d2307dea14a4 ("drm/atomic: use connector references (v3)")
Signed-off-by: Jon Hunter
---
drivers/gpu/drm/tegra/dsi.c | 16
1 file changed, 12 insertion
On 17/05/16 17:46, Daniel Vetter wrote:
> On Tue, May 17, 2016 at 05:27:15PM +0100, Jon Hunter wrote:
>> Commit d2307dea14a4 ("drm/atomic: use connector references (v3)") added
>> reference counting for DRM connectors and this caused a crash when
>> exercising sys
On 17/05/16 18:36, Daniel Vetter wrote:
> On Tue, May 17, 2016 at 7:29 PM, Jon Hunter wrote:
>>>> @@ -764,6 +769,9 @@ tegra_dsi_connector_duplicate_state(struct
>>>> drm_connector *connector)
>>>> if (!copy)
>>>>
or_destroy_state() in order to put the
reference for the connector.
Finally, add a warning if allocating memory for the state information
fails in tegra_dsi_connector_reset().
Fixes: d2307dea14a4 ("drm/atomic: use connector references (v3)")
Signed-off-by: Jon Hunter
---
V2 changes:
-
or_destroy_state() in order to put the
reference for the connector.
Fixes: d2307dea14a4 ("drm/atomic: use connector references (v3)")
Signed-off-by: Jon Hunter
Reviewed-by: Daniel Vetter
Acked-by: Thierry Reding
---
V3 changes:
- Dropped WARN_ON
V2 changes:
- Updated to next-20
On 12/05/16 13:21, Laxman Dewangan wrote:
> The IO pins of Tegra SoCs are grouped for common control of IO
> interface like setting voltage signal levels and power state of
> the interface. The group is generally referred as IO pads. The
> power state and voltage control of IO pins can be done at
On 19/05/16 17:13, Laxman Dewangan wrote:
> On Thursday 19 May 2016 09:24 PM, Jon Hunter wrote:
>> On 12/05/16 13:21, Laxman Dewangan wrote:
>>> The IO pins of Tegra SoCs are grouped for common control of IO
>>> interface like setting voltage signal levels and power
On 19/05/16 16:54, Jon Hunter wrote:
>
> On 12/05/16 13:21, Laxman Dewangan wrote:
>> The IO pins of Tegra SoCs are grouped for common control of IO
>> interface like setting voltage signal levels and power state of
>> the interface. The group is generally referred as IO
On 12/05/16 13:21, Laxman Dewangan wrote:
> The IO pins of Tegra SoCs are grouped for common control of IO
> interface like setting voltage signal levels and power state of
> the interface. The group is generally referred as IO pads. The
> power state and voltage control of IO pins can be done at
On 20/05/16 10:59, Laxman Dewangan wrote:
>
> On Friday 20 May 2016 03:32 PM, Jon Hunter wrote:
>> On 12/05/16 13:21, Laxman Dewangan wrote:
>> +#define TEGRA_IO_PADS_T124_T210(TEGRA_IO_PADS_T124 |\
>> +TEGRA_IO_PADS_T210)
>> +
>&
On 20/05/16 12:59, Laxman Dewangan wrote:
> The IO pins of Tegra SoCs are grouped for common control of IO
> interface like setting voltage signal levels and power state of
> the interface. The group is generally referred as IO pads. The
> power state and voltage control of IO pins can be done at
On 20/05/16 14:34, Laxman Dewangan wrote:
>
> On Friday 20 May 2016 07:02 PM, Jon Hunter wrote:
>> On 20/05/16 12:59, Laxman Dewangan wrote:
>>> +/* tegra_io_pads_config_info: Tegra IO pads bit config info.
>>> + * @dpd_config_bit: DPD configuration bit pos
On 20/05/16 14:34, Laxman Dewangan wrote:
>
> On Friday 20 May 2016 07:02 PM, Jon Hunter wrote:
>> On 20/05/16 12:59, Laxman Dewangan wrote:
>>> +/* tegra_io_pads_config_info: Tegra IO pads bit config info.
>>> + * @dpd_config_bit: DPD configuration bit pos
ra132 and Tegra210. The SOR
> driver is modified to use the new APIs.
>
> Signed-off-by: Laxman Dewangan
Thanks. I will defer to Thierry on how this should be organised for
merging but I am happy with the code. There is one minor typo below, but
otherwise ...
Acked-by: Jon Hunte
On 23/05/16 10:03, Jon Hunter wrote:
>
> On 20/05/16 15:45, Laxman Dewangan wrote:
>> The IO pins of Tegra SoCs are grouped for common control of IO
>> interface like setting voltage signal levels and power state of
>> the interface. The group is generally referred as IO
Hi Lee,
On 16/03/2020 09:05, Daniel Thompson wrote:
> On Fri, Mar 13, 2020 at 02:16:16PM +0000, Jon Hunter wrote:
>> Hi Lee, Daniel,
>>
>> On 24/02/2020 14:37, Daniel Thompson wrote:
>>> On Mon, Feb 24, 2020 at 02:07:48PM +, Jon Hunter wrote:
>>>> I
s: 2d9384ff9177 ("drm/tegra: Relax IOMMU usage criteria on old Tegra")
> Signed-off-by: Thierry Reding
> ---
> drivers/gpu/drm/tegra/drm.c | 3 ++-
> drivers/gpu/host1x/dev.c| 13 +
> include/linux/host1x.h | 3 +++
> 3 files changed, 18 ins
that all
> the system memory can be used for command buffers, irrespective of
> whether or not the host1x firewall is enabled.
>
> Signed-off-by: Thierry Reding
> ---
> drivers/gpu/host1x/dev.c | 46
> 1 file changed, 42 insertions(+), 4
names was not updated in the DP helper header file. Hence,
correct these names.
Signed-off-by: Jon Hunter
---
include/drm/drm_dp_helper.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 523f04c90dea..2e86f642f
The Display Port Auxiliary (DPAUX) channel pads can be shared with an
internal I2C controller. Add pinctrl support for these pads so that the
I2C controller can request and use these pads.
Jon Hunter (13):
drm/tegra: Clean-up if probing DPAUX fails
drm/tegra: Add helper functions for setting
modes, a case statement is used because when integrating with
the pinctrl framework, we need to be able to handle invalid modes that
could be passed.
Signed-off-by: Jon Hunter
---
drivers/gpu/drm/tegra/dpaux.c | 75 ++-
1 file changed, 45 insertions(+), 30
Update the DPAUX compatibility string information for Tegra124, Tegra132
and Tegra210. For Tegra210 an additional clock, 'sor-safe' is also
required for DPAUX and so add this clock information as well.
Signed-off-by: Jon Hunter
---
.../devicetree/bindings/display/tegra/nvidia,tegra20-
For Tegra210 the 'sor-safe' clock needs to be enabled when using DPAUX.
Add support to the DPAUX driver for enabling this clock on Tegra210.
Signed-off-by: Jon Hunter
---
drivers/gpu/drm/tegra/dpaux.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletion
: Jon Hunter
---
drivers/gpu/drm/tegra/dpaux.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index d696a7e45935..289bb064ca1e 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm
If the probing of the DPAUX fails, then clocks are left enabled and the
DPAUX reset de-asserted. Add code to perform the necessary clean-up on
probe failure by disabling clocks and asserting the reset.
Signed-off-by: Jon Hunter
---
drivers/gpu/drm/tegra/dpaux.c | 22 --
1
driver core by adding support for a
'i2c-bus' subnode where I2C slaves can be placed. If the 'i2c-bus'
subnode is present then all I2C slaves must be placed under this subnode.
Signed-off-by: Jon Hunter
---
Documentation/devicetree/bindings/i2c/i2c.txt | 8
1 file c
power-domain will be turned on before probing SOR or DPAUX
devices and kept on while the devices are bound.
Signed-off-by: Jon Hunter
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
b
The pinconf-generic.h file exposes functions for creating generic mappings
but it does not expose a function for freeing the mappings. Add a function
for freeing generic mappings.
Signed-off-by: Jon Hunter
---
drivers/pinctrl/pinconf-generic.c | 8
include/linux/pinctrl/pinconf
If the 'i2c-bus' device-tree node is present for an I2C adapter then
parse this subnode for I2C slaves.
Signed-off-by: Jon Hunter
---
drivers/i2c/i2c-core.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-co
roller binding document and add the 'i2c-bus' subnode. The 'i2c-bus'
subnode is used for populating I2C slaves for the DPAUX device so that
the I2C driver core does not attempt to add the DPAUX pad controller
nodes as I2C slaves.
Signed-off-by: Jon Hunter
---
.../display
The DPAUX pins are shared with an internal I2C controller. To allow
these pins to be muxed to the I2C controller, register a pinctrl device
for the DPAUX device. Make Tegra DRM support dependent on PINCTRL to
avoid any compilation issues.
Signed-off-by: Jon Hunter
---
drivers/gpu/drm/tegra
Populate the 'sor-safe' clock for DPAUX devices on Tegra210 that require
this clock for operation. Update the compatability string for the DPAUX
instance at address 0x545c to be "nvidia,tegra210-dpaux" to ensure
that the 'sor-safe' clock is enabled for this devi
fault, idle, etc) because the SOR driver will directly
set the state needed. For I2C clients only the I2C mode is used and so
we can simplify matters by using the generic pinctrl states for default
and idle.
Signed-off-by: Jon Hunter
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 48 ++
On 17/06/16 13:03, Jon Hunter wrote:
> The DPAUX pins are shared with an internal I2C controller. To allow
> these pins to be muxed to the I2C controller, register a pinctrl device
> for the DPAUX device. Make Tegra DRM support dependent on PINCTRL to
> avoid any compilation issues.
On 17/06/16 17:11, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Fri, Jun 17, 2016 at 01:03:36PM +0100, Jon Hunter wrote:
>> In preparation for adding pinctrl support for the DPAUX pads, add
>> helpers functions for configuring the pads and controlling the
On 17/06/16 17:13, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Fri, Jun 17, 2016 at 01:03:37PM +0100, Jon Hunter wrote:
>> Update the DPAUX compatibility string information for Tegra124, Tegra132
>> and Tegra210. For Tegra210 an additional clock, 'sor
On 17/06/16 17:18, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Fri, Jun 17, 2016 at 01:03:38PM +0100, Jon Hunter wrote:
>> For Tegra210 the 'sor-safe' clock needs to be enabled when using DPAUX.
>> Add support to the DPAUX driver for
On 17/06/16 17:24, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Fri, Jun 17, 2016 at 01:03:42PM +0100, Jon Hunter wrote:
>> If the 'i2c-bus' device-tree node is present for an I2C adapter then
>> parse this subnode for I2C slaves.
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