ondition))
> \
> __ret = __wait_event_hrtimeout(wq, condition, timeout,
> \
> -TASK_INTERRUPTIBLE);
> \
> +TASK_INTERRUPTIBLE,
> \
> +
a
> > different tree
> > (and it actually belongs to x86 if I got Ingo's comment right).
> > - Add in missing void return type in PATCH1 [Colin King, Ingo Molnar, Greg
> > KH]
> > - A few minor fixes in what is now PATCH7: add pr_fmt, tiny style fix in
> &
t; (and it actually belongs to x86 if I got Ingo's comment right).
> > - Add in missing void return type in PATCH1 [Colin King, Ingo Molnar, Greg
> > KH]
> > - A few minor fixes in what is now PATCH7: add pr_fmt, tiny style fix in
> > hyperv_flush_tlb_others(
* Vitaly Kuznetsov wrote:
> Ingo Molnar writes:
>
> > * Vitaly Kuznetsov wrote:
> >
> >> > Changes since v9:
> >> > - Rebase to 4.13-rc3.
> >> > - Drop PATCH1 as it was already taken by Greg to char-misc tree.
> >> > There&
* KY Srinivasan wrote:
>
>
> > -Original Message-
> > From: Dan Carpenter [mailto:dan.carpen...@oracle.com]
> > Sent: Saturday, September 9, 2017 4:04 AM
> > To: KY Srinivasan
> > Cc: x...@kernel.org; gre...@linuxfoundation.org; linux-
> > ker...@vger.kernel.org; de...@linuxdriverproj
* Arnd Bergmann wrote:
> This new 32-bit warning just showed up:
>
> arch/x86/hyperv/hv_init.c: In function 'hyperv_init':
> arch/x86/hyperv/hv_init.c:167:1: error: label 'register_msr_cs' defined but
> not used [-Werror=unused-label]
>
> The easiest solution is to move the label up into the
* k...@linuxonhyperv.com wrote:
> From: "K. Y. Srinivasan"
>
> The IPI hypercalls depend on being able to map the Linux notion of CPU ID
> to the hypervisor's notion of the CPU ID. The array hv_vp_index[] provides
> this mapping. Code for populating this array depends on the IPI functionality.
* KY Srinivasan wrote:
>
>
> > -Original Message-
> > From: Ingo Molnar On Behalf Of Ingo Molnar
> > Sent: Wednesday, July 4, 2018 9:11 AM
> > To: KY Srinivasan
> > Cc: x...@kernel.org; gre...@linuxfoundation.org; linux-
> > ker...@vger.k
* KY Srinivasan wrote:
>
>
> > -Original Message-
> > From: Ingo Molnar On Behalf Of Ingo Molnar
> > Sent: Thursday, July 5, 2018 8:38 AM
> > To: KY Srinivasan
> > Cc: x...@kernel.org; gre...@linuxfoundation.org; linux-
> > ker...@vger.k
* Thomas Gleixner wrote:
> On Fri, 6 Jul 2018, Ingo Molnar wrote:
> > * KY Srinivasan wrote:
> > > I am confused. The label ipi_mask_done was introduced in this patch
> > > (the patch under question fixes a circular dependency in this
hide places where vmalloc() et al are added to files
> but the include of vmalloc.h is forgotten.
Good idea.
Acked-by: Ingo Molnar
> Based in Linus' tree of today.
>
> There are probably more places that need vmalloc.h included, but this passes
> 64
> bit and 32 bit al
* Andy Lutomirski wrote:
> > What new syscalls would be needed for ssh to get all this support?
>
> This patchset or similar, plus some user code and an enclave to use.
>
> Sadly, on current CPUs, you also need Intel to bless the enclave. It looks
> like
> new CPUs might relax that requirem
;
> @@ -71,7 +71,7 @@ static void ac_status_changed(void)
>
> if (psy) {
> power_supply_changed(psy);
> - put_device(&psy->dev);
> + power_supply_put(psy);
> }
> }
Acked-by: Ingo Molnar
Thanks,
;
> @@ -93,7 +93,7 @@ static void ac_status_changed(void)
>
> if (psy) {
> power_supply_changed(psy);
> - put_device(&psy->dev);
> + power_supply_put(psy);
> }
> }
Acked-by: Ingo Molnar
Thanks,
* K. Y. Srinivasan wrote:
> If the hypervisor supports MSR based access to the APIC registers
> (EOI, TPR and ICR), implement the MSR based access.
>
> Signed-off-by: K. Y. Srinivasan
> ---
> arch/x86/include/uapi/asm/hyperv.h |5 +++
> arch/x86/kernel/cpu/mshyperv.c | 69
> +++
* K. Y. Srinivasan wrote:
> If the hypervisor supports MSR based access to the APIC registers
> (EOI, TPR and ICR), implement the MSR based access.
>
> Signed-off-by: K. Y. Srinivasan
> ---
> Changes from V1: Addressed comments from Ingo Molnar
>
You didn't a
16 matches
Mail list logo
