Greg,
> On 14 May 2018, at 10:02 pm, Greg Kroah-Hartman
> wrote:
>
> Can you please fix up the issues reported in this series, rebase on my
> latest tree, and resend so that I can apply them?
>
> thanks,
>
> greg k-h
I’m working on a version 2 patch set and will post when it is ready.
Jame
Dan,
> On 14 May 2018, at 11:47 pm, Dan Carpenter wrote:
>
> On Mon, May 07, 2018 at 11:20:29AM +1000, James Kelly wrote:
>> +static int clk_wzrd_probe(struct platform_device *pdev)
>> +{
>> +int ret;
>> +struct device *dev = &pdev->dev;
>>
quot;set-input-rate-range" allows the input rate to be
constrained to a narrower range than the hardware supports as this is
useful in some circumstances.
The input rate is then further constrained to ensure the PLL can always
lock when the input rate is changed.
Signed-off-by: James Kelly
---
d
now defaults to the least restrictive (fastest) speed grade.
Speed grade is now represented within the driver as an enum to enable
possible future support of non-integer speed grades, however it has not
been implemented here to avoid breaking the existing device tree bindings.
Signed-off-by: James Kell
divider.
Use DIV_ROUND_CLOSEST_ULL for division to provide best precision.
Signed-off-by: James Kelly
---
drivers/staging/clocking-wizard/TODO | 5 +-
.../clocking-wizard/clk-xlnx-clock-wizard.c| 68 --
2 files changed, 66 insertions(+), 7 deletions
Publish clock divider/multiplier ratios and flags specific to our
clock provider implementation as these are not available via the
debugfs entries provided by the common clock framework.
Signed-off-by: James Kelly
---
.../clocking-wizard/clk-xlnx-clock-wizard.c| 57
divider clock to ensure that
the PLL clock rate will remain within a valid range for the VCO, as it
is impossible to subsequently update any clock if the PLL does not lock.
A subsequent patch will address this issue.
Signed-off-by: James Kelly
---
drivers/staging/clocking-wizard/TODO
erty named "set-parent-output".
This is an optional property and if not present this feature is disabled.
If first divider clock is updated before the PLL multiplier clock adjust
the PLL multiplier to keep PLL lock.
Signed-off-by: James Kelly
---
drivers/staging/clocking-wizard/TODO
: James Kelly
---
.../clocking-wizard/clk-xlnx-clock-wizard.c| 53 ++
1 file changed, 53 insertions(+)
diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
index bb64da849d9b..c37f0e4451b4 100644
Add support for the clk_round_rate API to our CCF clock provider.
Signed-off-by: James Kelly
---
.../clocking-wizard/clk-xlnx-clock-wizard.c| 107 +
1 file changed, 107 insertions(+)
diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
b/drivers
directed
them to another Xilinx Linux maintainer.
James Kelly (14):
staging: clocking-wizard: Add principles of operation
staging: clocking-wizard: Reverse order of internal clocks
staging: clocking-wizard: Split probe function
staging: clocking-wizard: Cosmetic cleanups
staging
module unloading.
- regmap kernel APIs for memory mapped I/O. Regmap is also able to manage
prepare/enable/disable/unprepare of the AXI clock for us.
Note that use of the new CCF clock provider is deferred to a subsequent
patch.
Signed-off-by: James Kelly
---
.../clocking-wizard/clk-xlnx-clock
Add a description for how the Xilinx Clocking Wizard IP works to guide
subsequent patches.
Signed-off-by: James Kelly
---
.../clocking-wizard/clk-xlnx-clock-wizard.c| 52 ++
1 file changed, 52 insertions(+)
diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock
nitions easier to read
- Use #define for clock names in case we want to change them later
Signed-off-by: James Kelly
---
.../clocking-wizard/clk-xlnx-clock-wizard.c| 210 ++---
1 file changed, 105 insertions(+), 105 deletions(-)
diff --git a/drivers/staging/clocking-wizard/c
The order of the internal clocks does not match how the hardware
is arranged. We need to fix this before we can add new function.
Swap the order of the internal multiplier and divider clocks so that the
divider is the parent of the multiplier.
Signed-off-by: James Kelly
---
.../clocking
it used
undocumented register fields and it won't be needed anymore.
Signed-off-by: James Kelly
---
.../clocking-wizard/clk-xlnx-clock-wizard.c| 211 +++--
1 file changed, 71 insertions(+), 140 deletions(-)
diff --git a/drivers/staging/clocking-wizard/clk-xlnx-
Split probe function so that we can add more code in future patches
without it becoming too big.
Signed-off-by: James Kelly
---
.../clocking-wizard/clk-xlnx-clock-wizard.c| 63 +-
1 file changed, 51 insertions(+), 12 deletions(-)
diff --git a/drivers/staging
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