.
>
> Since this was the last user of the helper, it should now be safe to
> remove.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
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> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Thanks!
Maxime
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gt; configuration.
>
> Signed-off-by: Paul Kocialkowski
There's a couple of checkpatch --strict warnings here as well
Once fixed,
Acked-by: Maxime Ripard
Thanks!
Maxime
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d 10-bit Bayer formats are currently supported.
> While up to 4 internal channels to the CSI controller exist, only one
> is currently supported by this implementation.
>
> Signed-off-by: Paul Kocialkowski
CHECK: Alignment should match open parenthesis :)
Once fixed,
Acked-by: Maxime
On Thu, Dec 31, 2020 at 03:29:41PM +0100, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A31 MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
Reviewed-by: Maxime Ripard
Thanks!
Maxime
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hould not be linked in
> the fwnode graph unless they have a sensor subdev attached.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
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ated as fwnode port 0.
>
> Note that additional ports may be added in the future, especially to
> support feeding the CSI controller's output to the ISP.
>
> Signed-off-by: Paul Kocialkowski
> Reviewed-by: Rob Herring
Reviewed-by: Maxime Ripard
Maxim
On Fri, Dec 11, 2020 at 04:57:06PM +0100, Paul Kocialkowski wrote:
> The A83T supports MIPI CSI-2 with a composite controller, covering
> both the protocol logic and the D-PHY implementation. This controller
> seems to be found on the A83T only and probably was abandoned since.
>
> This implementa
On Fri, Dec 11, 2020 at 04:57:02PM +0100, Paul Kocialkowski wrote:
> +#define sun6i_mipi_csi2_subdev_video(subdev) \
> + container_of(subdev, struct sun6i_mipi_csi2_video, subdev)
> +
> +#define sun6i_mipi_csi2_video_dev(video) \
> + container_of(video, struct sun6i_mipi_csi2_dev, video)
I
On Fri, Dec 11, 2020 at 04:57:01PM +0100, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A31 MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
> ---
> .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 149 ++
> 1 file changed, 149 inserti
On Fri, Dec 11, 2020 at 04:57:00PM +0100, Paul Kocialkowski wrote:
> The A31 CSI controller supports a MIPI CSI-2 bridge input, which has
> its own dedicated port in the fwnode graph.
>
> Support for this input is added with this change:
> - two pads are defined for the media entity instead of one
On Wed, Dec 02, 2020 at 03:44:47PM +0100, Paul Kocialkowski wrote:
> > > +static int __maybe_unused sun6i_mipi_csi2_suspend(struct device *dev)
> > > +{
> > > + struct sun6i_mipi_csi2_dev *cdev = dev_get_drvdata(dev);
> > > +
> > > + clk_disable_unprepare(cdev->clk_mod);
> > > + clk_disable_unprepa
On Wed, Dec 02, 2020 at 04:02:09PM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Tue 01 Dec 20, 13:14, Maxime Ripard wrote:
> > On Sat, Nov 28, 2020 at 03:28:29PM +0100, Paul Kocialkowski wrote:
> > > Since the CSI controller binding is getting a bit more complex due
>
On Wed, Dec 02, 2020 at 03:19:11PM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Tue 01 Dec 20, 13:12, Maxime Ripard wrote:
> > Hi,
> >
> > On Sat, Nov 28, 2020 at 03:28:27PM +0100, Paul Kocialkowski wrote:
> > > The A31 CSI controller supports a MIPI CSI-2 b
Hi,
On Sat, Nov 28, 2020 at 03:28:33PM +0100, Paul Kocialkowski wrote:
> The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge
> found on Allwinner SoCs such as the A31 and V3/V3s.
>
> It is a standalone block, connected to the CSI controller on one side
> and to the MIPI D-PHY block on
On Sat, Nov 28, 2020 at 03:28:32PM +0100, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A31 MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
> ---
> .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 151 ++
> 1 file changed, 151 inserti
On Sat, Nov 28, 2020 at 03:28:29PM +0100, Paul Kocialkowski wrote:
> Since the CSI controller binding is getting a bit more complex due
> to the addition of MIPI CSI-2 bridge support, make the ports node
> explicit with the parallel port.
>
> This way, it's clear that the controller only supports
Hi,
On Sat, Nov 28, 2020 at 03:28:27PM +0100, Paul Kocialkowski wrote:
> The A31 CSI controller supports a MIPI CSI-2 bridge input, which has
> its own dedicated port in the fwnode graph.
>
> Support for this input is added with this change:
> - two pads are defined for the media entity instead o
On Sat, Nov 28, 2020 at 03:28:26PM +0100, Paul Kocialkowski wrote:
> The A31 CSI controller supports two distinct input interfaces:
> parallel and an external MIPI CSI-2 bridge. The parallel interface
> is often connected to a set of hardware pins while the MIPI CSI-2
> bridge is an internal FIFO-i
sun6i: Add support for Allwinner CSI V3s")
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
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is inspired by Allwinner's V3s Linux SDK
> implementation, which was used as a documentation base.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
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On Sat, Nov 28, 2020 at 03:28:21PM +0100, Paul Kocialkowski wrote:
> Besides giving pointers to the relevant functions for PHY mode and
> submode configuration, this clarifies the need to set them before
> powering on the PHY.
>
> Signed-off-by: Paul Kocialkowski
Reviewed-by
Hi Christoph,
On Thu, Nov 19, 2020 at 08:59:59AM +0100, Christoph Hellwig wrote:
> On Mon, Nov 09, 2020 at 10:43:03AM +0100, Maxime Ripard wrote:
> > Hi Christoph, Chen-Yu, Hans,
> >
> > On Fri, Nov 06, 2020 at 05:07:37PM +0100, Christoph Hellwig wrote:
> > > Thanks
Hi Christoph, Chen-Yu, Hans,
On Fri, Nov 06, 2020 at 05:07:37PM +0100, Christoph Hellwig wrote:
> Thanks,
>
> this looks good to me:
>
> Reviewed-by: Christoph Hellwig
>
> Can you include this patch at the end of your series to that it gets
> picked up with the other patches?
I guess the easi
vices.
Suggested-by: Robin Murphy
Signed-off-by: Maxime Ripard
---
drivers/soc/sunxi/Kconfig | 8 ++
drivers/soc/sunxi/Makefile | 1 +
drivers/soc/sunxi/sunxi_mbus.c | 132 +
3 files changed, 141 insertions(+)
create mode 100644 drivers/soc/sunxi/sunxi_m
of_dma_configure is called by the core before probe gets called so this
is redundant.
Signed-off-by: Maxime Ripard
---
drivers/media/platform/sunxi/sun8i-di/sun8i-di.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c
b/drivers/media
Hi,
Here's an attempt to removing the dma_direct_set_offset calls we have in
numerous drivers and move all those quirks into a global notifier as suggested
by Robin.
Let me know what you think,
Maxime
Maxime Ripard (7):
drm/sun4i: backend: Fix probe failure with multiple backends
soc:
Now that the MBUS quirks are applied by our global notifier, we can
remove them from Cedrus. Since the only quirk was whether or not we had
to apply that DMA quirk, we can also remove the quirks infrastructure.
Suggested-by: Christoph Hellwig
Signed-off-by: Maxime Ripard
---
drivers/staging
temporary measure to get it back working, before
removing that call entirely.
Fixes: e0d072782c73 ("dma-mapping: introduce DMA range map, supplanting
dma_pfn_offset")
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 8 +++-
1 file changed, 7 insertions(+),
Now that the MBUS quirks are applied by our global notifier, we can
remove them from our DRM driver.
Suggested-by: Christoph Hellwig
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/drivers/gpu/drm
Now that the MBUS quirks are applied by our global notifier, we can
remove them from our CSI driver for the A10.
Suggested-by: Christoph Hellwig
Signed-off-by: Maxime Ripard
---
.../platform/sunxi/sun4i-csi/sun4i_csi.c | 27 ---
1 file changed, 27 deletions(-)
diff --git
Now that the MBUS quirks are applied by our global notifier, we can
remove them from our CSI driver for the A31.
Suggested-by: Christoph Hellwig
Signed-off-by: Maxime Ripard
---
.../media/platform/sunxi/sun6i-csi/sun6i_csi.c | 17 -
1 file changed, 17 deletions(-)
diff --git
On Wed, Nov 04, 2020 at 12:34:58PM +0100, Paul Kocialkowski wrote:
> > > + regmap_write(regmap, SUN6I_MIPI_CSI2_CFG_REG,
> > > + SUN6I_MIPI_CSI2_CFG_CHANNEL_MODE(1) |
> > > + SUN6I_MIPI_CSI2_CFG_LANE_COUNT(lanes_count));
> >
> > It's not really clear what the channel is h
On Wed, Nov 04, 2020 at 01:38:08PM -0300, Helen Koike wrote:
>
>
> On 11/4/20 8:17 AM, Paul Kocialkowski wrote:
> > Hi,
> >
> > On Mon 02 Nov 20, 10:21, Maxime Ripard wrote:
> >> On Fri, Oct 30, 2020 at 07:45:18PM -0300, Helen Koike wrote:
> >>&
On Wed, Nov 04, 2020 at 11:48:27AM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Tue 27 Oct 20, 19:44, Maxime Ripard wrote:
> > On Tue, Oct 27, 2020 at 10:52:21AM +0100, Paul Kocialkowski wrote:
> > > Hi,
> > >
> > > On Mon 26 Oct 20, 17:14, Maxime Ripar
On Wed, Nov 04, 2020 at 10:15:49AM +, Robin Murphy wrote:
> On 2020-11-04 08:14, Maxime Ripard wrote:
> > Hi Christoph,
> >
> > On Tue, Nov 03, 2020 at 10:55:38AM +0100, Christoph Hellwig wrote:
> > > Linux 5.10-rc1 switched from having a single dma offset in s
Hi Christoph,
On Tue, Nov 03, 2020 at 10:55:38AM +0100, Christoph Hellwig wrote:
> Linux 5.10-rc1 switched from having a single dma offset in struct device
> to a set of DMA ranges, and introduced a new helper to set them,
> dma_direct_set_offset.
>
> This in fact surfaced that a bunch of drivers
On Mon, Nov 02, 2020 at 10:26:22PM +0800, Zhang Qilong wrote:
> pm_runtime_get_sync will increment pm usage counter even it
> failed. Forgetting to pm_runtime_put_noidle will result in
> reference leak in cedrus_start_streaming. We should fix it.
>
> Fixes: d5aecd289babf ("media: cedrus: Implement
On Fri, Oct 30, 2020 at 07:45:18PM -0300, Helen Koike wrote:
> On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> > The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 controller
> > found on Allwinner SoCs such as the A31 and V3/V3s.
> >
> > It is a standalone block, connected to the CSI control
Hi
On Fri, Oct 30, 2020 at 07:44:28PM -0300, Helen Koike wrote:
> On thing that is confusing me is the name csi2 with csi (that makes me
> think of csi vesun6i-csirsion one, which is not the case), I would
> rename it to sun6i-video (or maybe it is just me who gets confused).
>
> I know this drive
Hi!
On Fri, Oct 30, 2020 at 12:06:10PM +0100, Hans Verkuil wrote:
> Maxime,
>
> Are you OK with this series? It looks good to me.
I am, you can take it. I'll merge the dt patches through arm-soc
Thanks!
Maxime
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On Tue, Oct 27, 2020 at 10:52:21AM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Mon 26 Oct 20, 17:14, Maxime Ripard wrote:
> > i2c? :)
>
> Oops, good catch!
>
> > On Fri, Oct 23, 2020 at 07:45:39PM +0200, Paul Kocialkowski wrote:
> > > This introduces
On Tue, Oct 27, 2020 at 10:31:19AM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Mon 26 Oct 20, 17:00, Maxime Ripard wrote:
> > On Fri, Oct 23, 2020 at 07:45:37PM +0200, Paul Kocialkowski wrote:
> > > Bits related to the interface data width do not have any effect when
>
Hi,
On Tue, Oct 27, 2020 at 10:23:26AM +0100, Paul Kocialkowski wrote:
> On Mon 26 Oct 20, 16:38, Maxime Ripard wrote:
> > On Fri, Oct 23, 2020 at 07:45:34PM +0200, Paul Kocialkowski wrote:
> > > The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> >
On Fri, Oct 23, 2020 at 07:45:32PM +0200, Paul Kocialkowski wrote:
> This series introduces support for MIPI CSI-2, with the A31 controller that is
> found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific
> controller. While the former uses the same MIPI D-PHY that is already
>
On Fri, Oct 23, 2020 at 07:45:44PM +0200, Paul Kocialkowski wrote:
> The A83T supports MIPI CSI-2 with a composite controller, covering both the
> protocol logic and the D-PHY implementation. This controller seems to be found
> on the A83T only and probably was abandonned since.
>
> This implement
On Fri, Oct 23, 2020 at 07:45:46PM +0200, Paul Kocialkowski wrote:
> The A83T MIPI CSI-2 apparently produces interrupts regardless of the mask
> registers, for example when a transmission error occurs.
>
> This generates quite a flood when unsolicited interrupts are received on
> each received fra
On Fri, Oct 23, 2020 at 07:45:43PM +0200, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A83T MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
What is the difference with the a31/v3s one?
> ---
> .../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 158 +
On Fri, Oct 23, 2020 at 07:45:42PM +0200, Paul Kocialkowski wrote:
> MIPI CSI-2 is supported on the V3s with an A31 controller, which seems
> to be used on all Allwinner chips supporting it, except for the A83T.
> The controller is connected to CSI0 through fwnode endpoints.
> The mipi_csi2_in port
On Fri, Oct 23, 2020 at 07:45:40PM +0200, Paul Kocialkowski wrote:
> The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 controller
> found on Allwinner SoCs such as the A31 and V3/V3s.
>
> It is a standalone block, connected to the CSI controller on one side
> and to the MIPI D-PHY block on t
i2c? :)
On Fri, Oct 23, 2020 at 07:45:39PM +0200, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A31 MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
> ---
> .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 168 ++
> 1 file changed, 16
On Fri, Oct 23, 2020 at 07:45:37PM +0200, Paul Kocialkowski wrote:
> Bits related to the interface data width do not have any effect when
> the CSI controller is taking input from the MIPI CSI-2 controller.
I guess it would be clearer to mention that the data width is only
applicable for parallel
On Fri, Oct 23, 2020 at 07:45:35PM +0200, Paul Kocialkowski wrote:
> This allows selecting a dedicated CMA memory pool (specified via
> device-tree) instead of the default one.
>
> Signed-off-by: Paul Kocialkowski
Why would that be needed?
> ---
> drivers/media/platform/sunxi/sun6i-csi/sun6i_c
On Fri, Oct 23, 2020 at 07:45:34PM +0200, Paul Kocialkowski wrote:
> The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> is already supported and used for MIPI DSI this adds support for the
> former, to be used with MIPI CSI-2.
>
> This implementation is inspired by the Allwi
On Wed, Oct 21, 2020 at 10:33:25PM +0200, Jernej Skrabec wrote:
> If scaling matrix control is present, VPU should not use default matrix.
> Fix that.
>
> Fixes: b3a23db0e2f8 ("media: cedrus: Use H264_SCALING_MATRIX only when
> required")
> Signed-off-by: Jernej Skrab
On Thu, Sep 17, 2020 at 10:33:39AM +0200, Hans Verkuil wrote:
> Hi Maxime,
>
> On 27/08/2020 17:19, Maxime Ripard wrote:
> > On Tue, Aug 25, 2020 at 07:35:18PM +0200, Jernej Skrabec wrote:
> >> Allwinner R40 SoC contains video engine very similar to that in A33.
> &g
On Tue, Sep 08, 2020 at 06:44:06PM +0200, Martin Cerveny wrote:
> Hello.
>
> On Tue, 8 Sep 2020, Maxime Ripard wrote:
> > On Fri, Sep 04, 2020 at 10:01:06PM +0200, Martin Cerveny wrote:
> > > First patch extends cedrus capability to all decoders
> > >
On Fri, Sep 04, 2020 at 10:01:11PM +0200, Martin Cerveny wrote:
> Allwinner V3s SoC contains video engine. Add compatible for it.
>
> Signed-off-by: Martin Cerveny
The prefix isn't the right one, it shouldn't be media: but dt-bindings: media:
cedrus:
Maxime
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Hi,
On Fri, Sep 04, 2020 at 10:01:06PM +0200, Martin Cerveny wrote:
> First patch extends cedrus capability to all decoders
> because V3s missing MPEG2 decoder.
>
> Next two patches add system control node (SRAM C1) and
> next three patches add support for Cedrus VPU.
How was it tested?
Maxime
On Tue, Aug 25, 2020 at 07:35:18PM +0200, Jernej Skrabec wrote:
> Allwinner R40 SoC contains video engine very similar to that in A33.
>
> First two patches add system controller nodes and the rest of them
> add support for Cedrus VPU.
>
> Please take a look.
Applied all 5 patches, thanks
Maxim
me, can you please confirm
> that these two are still valid? They apply cleanly on the latest master
> at least, but since they are a bit old I prefer to have confirmation that
> it's OK to merge them.
Yes, you can definitely merge those.
Maxime
--
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Embedded Lin
On Mon, Jun 03, 2019 at 05:48:25PM +0200, Jernej Škrabec wrote:
> Dne ponedeljek, 03. junij 2019 ob 14:18:59 CEST je Maxime Ripard napisal(a):
> > > +static void cedrus_buf_cleanup(struct vb2_buffer *vb)
> > > +{
> > > + struct vb2_queue *vq = vb-
&output_buf->extra_buf_dma,
> +GFP_KERNEL);
> +
> + if (!output_buf->extra_buf)
> + output_buf->extra_buf_size = 0;
> + }
> +
That also means that inst
cedrus_buf->extra_buf_size,
> + cedrus_buf->extra_buf,
> + cedrus_buf->extra_buf_dma);
> + }
> +}
> +
I'm really not a fan of allocating something somewhere, and freeing it
somewhere else
On Thu, May 30, 2019 at 11:15:13PM +0200, Jernej Skrabec wrote:
> This array is just duplicated capture buffer queue. Remove it and adjust
> code to look into capture buffer queue instead.
>
> Signed-off-by: Jernej Skrabec
Acked-by: Maxime Ripard
Maxime
--
Maxime Ripard, Boot
udelay(1);
> + }
Can't we make that a bit simpler by not duplicating the loop?
Something like:
int current = 0;
while (current < num) {
int tmp = min(num - current, 32);
cedrus_write(dev, VE_H264_TRIGGER_TYPE, 0x3 | (current <&
..@ndufresne.ca
> Cc: boris.brezil...@collabora.com
> Cc: jo...@kwiboo.se
>
> Signed-off-by: Jernej Skrabec
Acked-by: Maxime Ripard
> ---
> We have to decide if we drop pps->num_ref_idx_l0_default_active_minus1
> and pps->num_ref_idx_l1_default_active_minus1 fields or
just remained disabled.
Maxime
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ate information.
>
> Signed-off-by: Jernej Skrabec
Acked-by: Maxime Ripard
Thanks!
Maxime
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ng. Maybe we could end with a spectrum of
> > capabilities that would allow us to cover the range from fully
> > stateless to fully stateful IPs more smoothly. Right now we have two
> > specifications that only consider the extremes of that range.
>
> I gave it a bit more
-specific structures. Can't we
> consider that in this specific instance, the hardware-specific
> structure just happens to be identical to the original bitstream
> format?
>
> I agree that this is not strictly optimal for that particular
> hardware, but such is the c
Hi,
On Thu, Jan 24, 2019 at 02:10:25PM +0100, Paul Kocialkowski wrote:
> On Tue, 2018-11-27 at 09:21 +0100, Maxime Ripard wrote:
> > Hi!
> >
> > On Fri, Nov 23, 2018 at 02:02:09PM +0100, Paul Kocialkowski wrote:
> > > This introduces support for HEVC/H.265
> > arm64: dts: allwinner: h5: Add Video Engine node
> > arm64: dts: allwinner: a64: Add Video Engine node
>
> Other than the error in patch 7,
>
> Acked-by: Chen-Yu Tsai
Applied all the patches but 11-13, with the changes discussed on patch 7 fixed.
On Wed, Dec 05, 2018 at 10:24:41AM +0100, Paul Kocialkowski wrote:
> Add the necessary compatible for supporting the H5 SoC along with a
> description of the capabilities of this variant.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
--
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65;5402;1c
On Wed, Dec 05, 2018 at 10:24:42AM +0100, Paul Kocialkowski wrote:
> Add the necessary compatible for supporting the A64 SoC along with a
> description of the capabilities of this variant.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
--
M
On Wed, Dec 05, 2018 at 10:24:40AM +0100, Paul Kocialkowski wrote:
> This introduces two new compatibles for the cedrus driver, for the
> A64 and H5 platforms.
>
> Signed-off-by: Paul Kocialkowski
> Reviewed-by: Rob Herring
Acked-by: Maxime Ripard
Maxime
--
Maxime Ripard, B
slice_params->dpb, slice_params->num_active_dpb_entries,
> + VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0);
> +
slice_params is enough.
> + if (pps->weighted_pred_flag || pps->weighted_bipred_flag)
> +
Hi,
On Fri, Nov 16, 2018 at 05:47:50PM +0800, Chen-Yu Tsai wrote:
> On Fri, Nov 16, 2018 at 5:39 PM Maxime Ripard
> wrote:
> >
> > On Thu, Nov 15, 2018 at 03:50:06PM +0100, Paul Kocialkowski wrote:
> > > Now that we have specific nodes for the H3 and H5 system-control
lly sure it's
relevant to mention it here.
> As a result, remove the global IRQ spin lock.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
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a reg register.
I've fixed it in the other DT by renaming that node to
default-pool. You can also drop the label, it's not used anywhere.
Maxime
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};
> -
You're also dropping the syscon compatible there. But I'm not sure how
it could work with the H3 EMAC driver that would overwrite the
compatible already.
Maxime
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Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
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>
> Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
>
> Fixes: 50e761516f2b ("media: platform: Add Cedrus VPU decoder driver")
> CC: Paul Kocialkowski
> Signed-off-by: kbuild test robot
Acked-by: Maxime Ripard
Thanks!
Maxime
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Maxime Ripard, Bootl
'ctx->ctrls'. (kzalloc returns null)
>
> The problem is that it assumes that kzalloc() will always
> succeed.
>
> Signed-off-by: Mauro Carvalho Chehab
Acked-by: Maxime Ripard
Thanks!
Maxime
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Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://boot
unt,
> this way ctxt will be non-null hence avoiding the null pointer
> dereference.
>
> Detected by CoverityScan, CID#1475337 ("Explicit null dereferenced")
>
> Fixes: 50e761516f2b ("media: platform: Add Cedrus VPU decoder driver")
> Signed-off-by: C
ction?
>
> Also what is the status of adding this driver to say staging?
IIRC, we tried to get it into staging, and we got told that it was too
nice for staging at this point. So we're basically stuck somewhere
between staging and !staging, with the driver being too nice for the
former, and not nice enough for the latter :)
Maxime
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Embedded Linux and Kernel engineering
https://bootlin.com
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inux-sunxi community in the interest of reverse
> > engineering, documenting and implementing support for the Allwinner VPU.
> >
> > Signed-off-by: Paul Kocialkowski
> > Acked-by: Maxime Ripard
>
> There are several checkpatch issues here. Ok, some can be
> ignored
multi-planar tiled YUV format (based on NV12). A specific
> format is introduced in the V4L2 API to describe it. Starting with the
> A33, the Video Engine can also output untiled YUV formats.
Applied the DTS patches, thanks!
Maxime
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Maxime Ripard, Bootlin
Embedded Linux and Kernel engineerin
On Fri, Sep 07, 2018 at 03:52:00PM +0200, Hans Verkuil wrote:
> On 09/07/2018 03:26 PM, Maxime Ripard wrote:
> > Hi Hans,
> >
> > On Fri, Sep 07, 2018 at 03:13:19PM +0200, Hans Verkuil wrote:
> >> On 09/07/2018 12:24 AM, Paul Kocialkowski wrote:
> >>>
n the interest of reverse
> > engineering, documenting and implementing support for the Allwinner VPU.
> >
> > Signed-off-by: Paul Kocialkowski
> > Acked-by: Maxime Ripard
>
> One high-level comment:
>
> Can you add a TODO file for this staging driver? This can
dst_luma_addr,
> + dst_chroma_addr);
> + }
> +}
You have this a number of times, but you can reduce the range of most
of the variables (basically all of them but dev and i) to the loop
itself. Declaring them for the whole function like you
frame.
>
> This driver was made possible thanks to the long-standing effort
> carried out by the linux-sunxi community in the interest of reverse
> engineering, documenting and implementing support for Allwinner VPU.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
so the reserved memory
> pool has to be located in that area. Following Allwinner's decision in
> downstream software, the last 96 MiB of the first 256 MiB of RAM are
> reserved for this purpose.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
--
Maxime
On Tue, Aug 28, 2018 at 09:34:24AM +0200, Paul Kocialkowski wrote:
> This adds nodes for the Video Engine and the associated reserved memory
> for the H3. Up to 96 MiB of memory are dedicated to the CMA pool.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
y
> pool has to be located in that area. Following Allwinner's decision in
> downstream software, the last 96 MiB of the first 256 MiB of RAM are
> reserved for this purpose.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
--
Maxime Ripard, Bootlin
Embed
y
> pool has to be located in that area. Following Allwinner's decision in
> downstream software, the last 96 MiB of the first 256 MiB of RAM are
> reserved for this purpose.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
--
Maxime Ripard, Bootlin
Embed
On Tue, Aug 28, 2018 at 09:34:19AM +0200, Paul Kocialkowski wrote:
> This adds a device-tree binding document that specifies the properties
> used by the Cedurs VPU driver, as well as examples.
>
> Signed-off-by: Paul Kocialkowski
> Reviewed-by: Rob Herring
Acked-by: Maxime R
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