Friday, October 27, 2017 5:30 PM
> > > To: Bogdan Purcareata <bogdan.purcare...@nxp.com>
> > > Cc: Ruxandra Ioana Radulescu <ruxandra.radule...@nxp.com>;
> > > gre...@linuxfoundation.org; linux-ker...@vger.kernel.org;
> > > de...@driverdev.osuosl.org
> &g
t; > Cc: Ruxandra Ioana Radulescu <ruxandra.radule...@nxp.com>;
> > gre...@linuxfoundation.org; linux-ker...@vger.kernel.org;
> > de...@driverdev.osuosl.org
> > Subject: Re: [PATCH 4/5] staging: fsl-dpaa2/eth: Change RX buffer alignment
> >
> > On Fri, Oct 27, 20
; linux-ker...@vger.kernel.org;
> de...@driverdev.osuosl.org
> Subject: Re: [PATCH 4/5] staging: fsl-dpaa2/eth: Change RX buffer alignment
>
> On Fri, Oct 27, 2017 at 02:11:35PM +, Bogdan Purcareata wrote:
> > @@ -93,10 +100,10 @@
> > * buffers large enough t
On Fri, Oct 27, 2017 at 02:11:35PM +, Bogdan Purcareata wrote:
> @@ -93,10 +100,10 @@
> * buffers large enough to allow building an skb around them and also account
> * for alignment restrictions
> */
> -#define DPAA2_ETH_BUF_RAW_SIZE \
> +#define DPAA2_ETH_BUF_RAW_SIZE(priv) \
>
The WRIOP hardware block v1.0.0 (found on LS2080A board)
requires data in RX buffers to be aligned to 256B, but
newer revisions (e.g. on LS2088A, LS1088A) only require
64B alignment.
Check WRIOP version and decide at runtime which alignment
requirement to configure for ingress buffers.