Hi Dan,
On Mon, Nov 30, 2020 at 1:15 PM Dan Carpenter wrote:
>
> On Thu, Nov 19, 2020 at 07:05:22AM +0100, Sergio Paracuellos wrote:
> > > > +static inline void phy_write(struct mt7621_pci_phy *phy, u32 val, u32
> > > > reg)
> > > > +{
> > > > + regmap_write(phy->regmap, reg, val);
> > >
>
On Thu, Nov 19, 2020 at 07:05:22AM +0100, Sergio Paracuellos wrote:
> > > +static inline void phy_write(struct mt7621_pci_phy *phy, u32 val, u32
> > > reg)
> > > +{
> > > + regmap_write(phy->regmap, reg, val);
> >
> > Why not use regmap_ calls directly and avoid the dummy wrappers..?
>
>
Hi Vinod,
Thanks for the review.
On Thu, Nov 19, 2020 at 6:31 AM Vinod Koul wrote:
>
> On 31-10-20, 13:22, Sergio Paracuellos wrote:
>
> > +#define RG_PE1_PIPE_REG 0x02c
> > +#define RG_PE1_PIPE_RST BIT(12)
> > +#define
On 31-10-20, 13:22, Sergio Paracuellos wrote:
> +#define RG_PE1_PIPE_REG 0x02c
> +#define RG_PE1_PIPE_RST BIT(12)
> +#define RG_PE1_PIPE_CMD_FRC BIT(4)
> +
> +#define RG_P0_TO_P1_WIDTH0x100
> +#define
This patch adds a driver for the PCIe PHY of MT7621 SoC.
Signed-off-by: Sergio Paracuellos
---
drivers/phy/ralink/Kconfig | 8 +
drivers/phy/ralink/Makefile | 1 +
drivers/phy/ralink/phy-mt7621-pci.c | 373
3 files changed, 382 insertions(+)
