Cc: Shumin Qiu
Cc: Michael Kinney
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/UefiCpuPkg.uni | Bin 21898 -> 22498 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/UefiCpuPkg/UefiCpuPkg.uni b/UefiCpuPkg/UefiCpuPkg.uni
index
Reviewed-by: Qiu Shumin
-Original Message-
From: Fan, Jeff
Sent: Wednesday, December 09, 2015 2:57 PM
To: edk2-devel@lists.01.org
Cc: Qiu, Shumin; Kinney, Michael D
Subject: [Patch] UefiCpuPkg/MtrrLib:Initialize local variables before use them
Cc: Shumin Qiu
Cc: Michael Kinney
Contrib
Cc: Shumin Qiu
Cc: Michael Kinney
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
b/UefiCpuPkg/Library/MtrrLib/Mt
Cc: Shuming Qiu
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/CpuMpPei/CpuMpPei.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.c b/UefiCpuPkg/CpuMpPei/CpuMpPei.c
index ab1260d..2e6e761 100644
In multiple root bridge platforms, different root bridges may
share the same segment but occupy different range of buses,
or may occupy different segments.
The fix is to find the correct root bridge IO instance by
comparing not only the segment but also the bus ranges.
It tries to access the MMIO a
Mike,
Please check the updated patch which adopted your comments.
Regards,
Ray
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Ruiyu Ni
Sent: Wednesday, December 9, 2015 2:36 PM
To: edk2-devel@lists.01.org
Cc: Ni, Ruiyu ; Kinney, Michael D
; Tia
PciSioSerialDxe driver can manages UARTs on a SIO chip or a PCI/PCIE
card.
It manages the SIO instance whose last device path node is a ACPI
device path and the HID in the ACPI device path node equals to
EISA_PNP_ID (0x501).
It also manages the PCI IO instance whose class code is 7/0/2 (16550
UART)
Zach:
Tool chain family will filter the source files those don't target for it. For
your case, EnablePaging32.S will only be selected.
Thanks
Liming
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Zachary
Bobroff
Sent: Wednesday, December 09,
Ray,
In general the code changes looks really good. The CPU I/O protocols is only
conditionally used, so the INF should be SOMETIMES_CONSUMES for that protocol.
I can not apply the patch because of an issue with UNI file to try running it.
Can you please try regenerating the patch against the
This patch is used to fix the potential NULL pointer dereferenced
in function 'ParseDnsResponse'.
Cc: Fu Siyuan
Cc: Zhang Lubo
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu
---
NetworkPkg/DnsDxe/DnsImpl.c | 59 +++--
1
Ray,
This works much better now. I have a couple comments:
1) The #define for SERIAL_MAX_BUFFER_SIZE was removed. This is the size of a
software FIFO to manage data sent to the Serial I/O Protocol. This value is
not the same as the size of the HW FIFO in the UART. I recommend we keep the
#
Reviewed-by: Liming Gao
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Ard
Biesheuvel
Sent: Monday, December 07, 2015 6:08 PM
To: edk2-devel@lists.01.org; Cohen, Eugene
Cc: Ard Biesheuvel; Laszlo Ersek; Leif Lindholm; Gao, Liming
Subject: Re: [e
Hi Eugene,
Thanks for the updated patch, but it seems not resolve my concern.
On 2015/12/8 22:42, Cohen, Eugene wrote:
[This patch is updated from v1 to defer publication of the decompression and
extraction PPIs
until after permanent memory is installed. Tested for normal boots and our
temp
All,
I have noticed the addition of the BUILDRULEORDER option and it looks quite
powerful based upon the information in the Build Specification. The only
question I have is how does it handle files that are already flagged for a
specific toolchain family? For example:
*_*_*_*_BUILDRULEORDER
Thanks for your well-thought out and detailed answer !I guess the safe bet is
"No". Stay away from floating point on EDK2.
Shubha Shubha D. ramanishubharam...@gmail.com
shubharam...@yahoo.com
On Saturday, December 5, 2015 4:24 PM, Scott Duplichan
wrote:
Daryl McDaniel [mailto:edk2-li.
On 8 December 2015 at 16:49, Leif Lindholm wrote:
> On Tue, Dec 08, 2015 at 04:19:47PM +0100, Ard Biesheuvel wrote:
>> On 8 December 2015 at 14:05, Cohen, Eugene wrote:
>> > Reviewed-by: Eugene Cohen
>> >
>>
>> Thanks Eugene
>>
>> @Leif: any concerns?
>
> None - just stuck in a meeting :)
> Than
On Tue, Dec 08, 2015 at 04:19:47PM +0100, Ard Biesheuvel wrote:
> On 8 December 2015 at 14:05, Cohen, Eugene wrote:
> > Reviewed-by: Eugene Cohen
> >
>
> Thanks Eugene
>
> @Leif: any concerns?
None - just stuck in a meeting :)
Thanks.
Reviewed-by: Leif Lindholm
> >> -Original Message---
On 8 December 2015 at 14:05, Cohen, Eugene wrote:
> Reviewed-by: Eugene Cohen
>
Thanks Eugene
@Leif: any concerns?
>> -Original Message-
>> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
>> Sent: Monday, December 07, 2015 12:06 AM
>> To: edk2-devel@lists.01.org; leif.lindh...
Commit SVN r18778 made all mappings of normal memory (inner) shareable,
even on hardware that implements shareability as uncached accesses.
The original concerns that prompted the change, regarding coherent DMA
and virt guests migrating between CPUs, do not apply to such hardware,
so revert to the
[This patch is updated from v1 to defer publication of the decompression and
extraction PPIs
until after permanent memory is installed. Tested for normal boots and our
temporary
memory S3 resume path.]
This enable S3 resume from temporary memory. The normal boot path
still enforces the permane
Although I agree with the logic, I would like to see the magic numbers replaced
with #defines.
> + switch ((Mmfr >> 12) & 0xf) {
For maintainability and isolation purposes I expect that we would have a header
file (or files) for architectural defines like MMFR0 definitions. In this case
I wo
On 8 December 2015 at 15:06, Leif Lindholm wrote:
> On Tue, Dec 08, 2015 at 11:17:33AM +0100, Ard Biesheuvel wrote:
>> Now that we removed the complete ArmPlatformGlobalVariable implementation,
>> remove stale PCD references to it from ArmVExpress-CTA15-A7.dsc
>>
>> Contributed-under: TianoCore Co
On Tue, Dec 08, 2015 at 03:03:05PM +0100, Ard Biesheuvel wrote:
> Commit SVN r18778 made all mappings of normal memory (inner) shareable,
> even on hardware that implements shareability as uncached accesses.
> The original concerns that prompted the change, regarding coherent DMA
> and virt guests
On 8 December 2015 at 15:09, Leif Lindholm wrote:
> On Tue, Dec 08, 2015 at 09:57:40AM +0100, Ard Biesheuvel wrote:
>> RVCT does not like the arithmetic involving a VOID* pointer that was
>> introduced in SVN r19163, so use explicit casts instead.
>>
>> Contributed-under: TianoCore Contribution Ag
On Tue, Dec 08, 2015 at 09:57:40AM +0100, Ard Biesheuvel wrote:
> RVCT does not like the arithmetic involving a VOID* pointer that was
> introduced in SVN r19163, so use explicit casts instead.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel
Reviewed-b
On Tue, Dec 08, 2015 at 11:17:33AM +0100, Ard Biesheuvel wrote:
> Now that we removed the complete ArmPlatformGlobalVariable implementation,
> remove stale PCD references to it from ArmVExpress-CTA15-A7.dsc
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel
Commit SVN r18778 made all mappings of normal memory (inner) shareable,
even on hardware that implements shareability as uncached accesses.
The original concerns that prompted the change, regarding coherent DMA
and virt guests migrating between CPUs, do not apply to such hardware,
so revert to the
Dear Expert,
According to compiler setting in "BaseTools\Source\C\Makefiles\ms.common"
and "BaseTools\Source\C\Makefiles\ms.app", the target win32 base tools are
debug version, could we update this compiler flag to build release version
tools? Is there any known issue?
Thanks.
CFLAGS =
On 8 December 2015 at 14:05, Cohen, Eugene wrote:
> I'd like to dig up this thread because I suspect there's something that is
> fundamentally misunderstood.
>
> On at least one older non-MP processor (Cortex-A8) this change just forces
> all accesses to be uncached - this is true for L1 I+D and
Integrated all four patches, including the not yet committed patch #4 (as of
yesterday, not counting the latest update where the warning suppression was
moved).
Reviewed-by: Eugene Cohen
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf
> Of Coh
On 8 December 2015 at 14:05, Cohen, Eugene wrote:
> I'd like to dig up this thread because I suspect there's something that is
> fundamentally misunderstood.
>
> On at least one older non-MP processor (Cortex-A8) this change just forces
> all accesses to be uncached - this is true for L1 I+D and
Reviewed-by: Eugene Cohen
> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: Monday, December 07, 2015 12:06 AM
> To: edk2-devel@lists.01.org; leif.lindh...@linaro.org; Cohen, Eugene
>
> Cc: Ard Biesheuvel
> Subject: [PATCH] ArmPkg: update InvalidateI
I'd like to dig up this thread because I suspect there's something that is
fundamentally misunderstood.
On at least one older non-MP processor (Cortex-A8) this change just forces all
accesses to be uncached - this is true for L1 I+D and L2. There's nothing
strange about the L2 subsystem or bus
Now that we removed the complete ArmPlatformGlobalVariable implementation,
remove stale PCD references to it from ArmVExpress-CTA15-A7.dsc
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel
---
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.dsc | 10 ---
PciSioSerialDxe driver can manages UARTs on a SIO chip or a PCI/PCIE
card.
It manages the SIO instance whose last device path node is a ACPI
device path and the HID in the ACPI device path node equals to
EISA_PNP_ID (0x501).
It also manages the PCI IO instance whose class code is 7/0/2 (16550
UART)
RVCT does not like the arithmetic involving a VOID* pointer that was
introduced in SVN r19163, so use explicit casts instead.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel
---
ArmPlatformPkg/PrePeiCore/MainMPCore.c | 2 +-
ArmPlatformPkg/PrePeiCore/MainUn
The RVCT compiler chokes on a couple of issues in upstream OpenSSL that
can be confirmed to be non-issues by inspection. So just ignore these
warnings entirely.
Also, move the dummy -J system include from CryptoPkg.dsc to the various
.INF files, since it will not be picked up when building the Cry
On 8 December 2015 at 08:50, Ard Biesheuvel wrote:
> On 7 December 2015 at 14:32, Cohen, Eugene wrote:
>> Ard,
>>
>>> As far as patch #4 is concerned, let's wait for confirmation from Eugene,
>>> also
>>> regarding the issue of reporting defect against RVCT (if there is a point in
>>> doing so)
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