This path is used to standardize TLS definitions from related
RFCs. Including TLS Cipher Suites, TLS Version, TLS Content Type
and TLS Record Header, etc.
Cc: Liming Gao
Cc: Palmer Thomas
Cc: Long Qin
Cc: Ye Ting
Cc: Palmer Thomas
Cc: Long Qin
Cc: Ye Ting
Cc: Fu Siyuan
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu Jiaxin
Signed-off-by: Jiaxin Wu
---
Cc: Palmer Thomas
Cc: Long Qin
Cc: Ye Ting
Cc: Fu Siyuan
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu Jiaxin
Signed-off-by: Jiaxin Wu
---
This patch is used to add more TLS cipher suite mapping between
Cipher Suite definitions and OpenSSL-used Cipher Suite name.
Cc: Palmer Thomas
Cc: Long Qin
Cc: Ye Ting
Contributed-under: TianoCore Contribution Agreement 1.0
The series patches are used to replace the TLS definitions with the
standardized one. In addition, more TLS cipher suite mapping between
Cipher Suite definitions and OpenSSL-used Cipher Suite name are added.
Cc: Liming Gao
Cc: Palmer Thomas
Cc: Long
Reviewed-by: Giri P Mudusuru
> -Original Message-
> From: Gao, Liming
> Sent: Wednesday, July 13, 2016 7:16 PM
> To: edk2-devel@lists.01.org
> Cc: Mudusuru, Giri P ; Yao, Jiewen
>
> Subject: [Patch]
PlatformSecLib.h is not used and removed.
Cc: Giri P Mudusuru
Cc: Jiewen Yao
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao
---
IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c | 1 -
Fixed typo: *add* whitespace. :-)
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Fan, Jeff
Sent: Thursday, July 14, 2016 9:15 AM
To: Mudusuru, Giri P; edk2-de...@ml01.01.org
Cc: Kinney, Michael D; Tian, Feng
Subject: Re: [edk2] [Patch v3 4/7]
Thanks! I will add one whitespace before eax in comments when commit.
-Original Message-
From: Mudusuru, Giri P
Sent: Wednesday, July 13, 2016 11:21 PM
To: Fan, Jeff; edk2-de...@ml01.01.org
Cc: Tian, Feng; Kinney, Michael D
Subject: RE: [Patch v3 2/7] UefiCpuPkg/CpuMpPei/Ia32: Use
Thanks! I will remove white space after "," in comments when commit.
-Original Message-
From: Mudusuru, Giri P
Sent: Wednesday, July 13, 2016 11:42 PM
To: Fan, Jeff; edk2-de...@ml01.01.org
Cc: Tian, Feng; Kinney, Michael D
Subject: RE: [Patch v3 4/7] UefiCpuPkg/CpuMpPei/X64: Use
Reviewed-by: Jeff Fan
-Original Message-
From: Laszlo Ersek [mailto:ler...@redhat.com]
Sent: Wednesday, July 13, 2016 10:37 PM
To: edk2-devel-01
Cc: Fan, Jeff; Justen, Jordan L; Kinney, Michael D
Subject: [PATCH v3 0/5] OvmfPkg: program MSR_IA32_FEATURE_CONTROL from
Reviewed-by: Jeff Fan
-Original Message-
From: Laszlo Ersek [mailto:ler...@redhat.com]
Sent: Wednesday, July 13, 2016 10:37 PM
To: edk2-devel-01
Cc: Fan, Jeff; Justen, Jordan L; Kinney, Michael D
Subject: [PATCH v3 4/5] OvmfPkg: include UefiCpuPkg/CpuMpPei
In the
Brian,
Good point on BSP bit in MSR_IA32_APIC_BASE register. But some processor(for
example, Quark) does not support this MSR.
//
// CPUs with a FamilyId of 0x04 or 0x05 do not support the
// Local APIC Base Address MSR
//
I think the generic solution is still to remove MTRRs
> On Jul 13, 2016, at 5:42 PM, Gao, Liming wrote:
>
> Reviewed-by: Liming Gao
>
Reviewed-by: Andrew Fish
>> -Original Message-
>> From: Zhu, Yonghong
>> Sent: Monday, July 11, 2016 4:10 PM
>> To: edk2-devel@lists.01.org
Reviewed-by: Liming Gao
> -Original Message-
> From: Zhu, Yonghong
> Sent: Monday, July 11, 2016 4:10 PM
> To: edk2-devel@lists.01.org
> Cc: Gao, Liming
> Subject: [Patch] BaseTools: Update the FV region name as upper letter
>
> Since in the
On 07/13/16 22:31, Ard Biesheuvel wrote:
> On 13 July 2016 at 22:17, Laszlo Ersek wrote:
>> On 07/13/16 22:03, Ard Biesheuvel wrote:
>>> On 13 July 2016 at 18:44, Laszlo Ersek wrote:
+DEBUG_CODE (
+ CHAR16 *DevicePathString;
+
+
On 13 July 2016 at 22:17, Laszlo Ersek wrote:
> On 07/13/16 22:03, Ard Biesheuvel wrote:
>> On 13 July 2016 at 18:44, Laszlo Ersek wrote:
>>> (This patch ports OvmfPkg commit 2eb358986052 to ArmVirtPkg. That
>>> functionality was not added to
On 07/13/16 22:03, Ard Biesheuvel wrote:
> On 13 July 2016 at 18:44, Laszlo Ersek wrote:
>> (This patch ports OvmfPkg commit 2eb358986052 to ArmVirtPkg. That
>> functionality was not added to QemuBootOrderLib, because it was (and is)
>> independent from QEMU and fw_cfg.)
>>
>>
On 13 July 2016 at 18:44, Laszlo Ersek wrote:
> (This patch ports OvmfPkg commit 2eb358986052 to ArmVirtPkg. That
> functionality was not added to QemuBootOrderLib, because it was (and is)
> independent from QEMU and fw_cfg.)
>
> Remove any boot options that point to binaries
On 07/13/2016 11:19 AM, Laszlo Ersek wrote:
On 07/13/16 17:46, Kinney, Michael D wrote:
Laszlo,
I agree that the DEBUG() messages for this are very valuable to debug
MTRR cache settings.
Another option is to add logic to detect if the calling CPU is the BSP or
not and only invoke DEBUG()
(This patch ports OvmfPkg commit 2eb358986052 to ArmVirtPkg. That
functionality was not added to QemuBootOrderLib, because it was (and is)
independent from QEMU and fw_cfg.)
Remove any boot options that point to binaries built into the firmware and
have become stale due to any of the following:
-
On 07/13/16 18:13, Kinney, Michael D wrote:
> Hi Laszlo,
>
> I missed this other part of this thread. I agree with the direction here.
>
> Reviewed-by: Michael Kinney
>
> If anyone notices a loss of messages from BSP when DEBUG_CACHE is enabled,
> then the correct
On 07/13/16 17:46, Kinney, Michael D wrote:
> Laszlo,
>
> I agree that the DEBUG() messages for this are very valuable to debug
> MTRR cache settings.
>
> Another option is to add logic to detect if the calling CPU is the BSP or
> not and only invoke DEBUG() macros if the caller is the BSP.
Hi Laszlo,
I missed this other part of this thread. I agree with the direction here.
Reviewed-by: Michael Kinney
If anyone notices a loss of messages from BSP when DEBUG_CACHE is enabled,
then the correct fix is to add an explicit call to MtrrDebugPrintAllMtrrs().
On 13 July 2016 at 16:35, Ard Biesheuvel wrote:
> On 8 July 2016 at 10:42, Shi, Steven wrote:
>> Both GCC and LLVM 3.8 64bits support new variable argument (VA)
>> intrinsics for Microsoft ABI, enable these new VA intrinsics for
>> GNUC family
Laszlo,
I agree that the DEBUG() messages for this are very valuable to debug
MTRR cache settings.
Another option is to add logic to detect if the calling CPU is the BSP or
not and only invoke DEBUG() macros if the caller is the BSP. That would
not require any changes to the MtrrLib APIs or
> On Jul 13, 2016, at 8:05 AM, Ard Biesheuvel wrote:
>
> On 12 July 2016 at 19:33, Andrew Fish wrote:
>>
>>> On Jul 12, 2016, at 9:55 AM, Ard Biesheuvel
>>> wrote:
> [...]
>>> OK, so in summary, the AMD64 small model not
Reviewed-by: Giri P Mudusuru
> -Original Message-
> From: Fan, Jeff
> Sent: Tuesday, July 12, 2016 4:45 AM
> To: edk2-de...@ml01.01.org
> Cc: Tian, Feng ; Kinney, Michael D
> ; Mudusuru, Giri P
>
Reviewed-by: Giri P Mudusuru
> -Original Message-
> From: Fan, Jeff
> Sent: Tuesday, July 12, 2016 4:45 AM
> To: edk2-de...@ml01.01.org
> Cc: Tian, Feng ; Kinney, Michael D
> ; Mudusuru, Giri P
>
Reviewed-by: Giri P Mudusuru
> -Original Message-
> From: Fan, Jeff
> Sent: Tuesday, July 12, 2016 4:44 AM
> To: edk2-de...@ml01.01.org
> Cc: Tian, Feng ; Kinney, Michael D
> ; Mudusuru, Giri P
>
Reviewed-by: Giri P Mudusuru
Please review and add white space after "," in comments during submission
> -Original Message-
> From: Fan, Jeff
> Sent: Tuesday, July 12, 2016 4:44 AM
> To: edk2-de...@ml01.01.org
> Cc: Tian, Feng ; Kinney,
On 07/13/16 08:26, Michael Kinney wrote:
> This patch series fixes a number of small issues in the S3 resume path.
>
> * Remove duplicate aligned buffer allocation on S3 resume path
> * Add support for MemoryMapped REGISTER_TYPE in SetProcessorRegister()
> * Move XD/BTS feature detection to
Reviewed-by: Giri P Mudusuru
> -Original Message-
> From: Fan, Jeff
> Sent: Tuesday, July 12, 2016 4:44 AM
> To: edk2-de...@ml01.01.org
> Cc: Tian, Feng ; Kinney, Michael D
> ; Mudusuru, Giri P
>
Reviewed-by: Giri P Mudusuru
Please add a whitespace before eax in the comments during submission.
mov[di],eax
> -Original Message-
> From: Fan, Jeff
> Sent: Tuesday, July 12, 2016 4:44 AM
> To: edk2-de...@ml01.01.org
> Cc: Tian, Feng
Reviewed by: jiewen@intel.com
> -Original Message-
> From: Yarlagadda, Satya P
> Sent: Wednesday, July 13, 2016 9:03 PM
> To: edk2-devel@lists.01.org
> Cc: Mudusuru, Giri P ; Yao, Jiewen
>
> Subject: [PATCH]
On 13 July 2016 at 17:00, Laszlo Ersek wrote:
> On 07/13/16 16:55, Ard Biesheuvel wrote:
>> The E820EntriesCount variable in XenPublishRamRegions() may be
>> referenced without being initialized on RELEASE builds, since the
>> ASSERT that fires if the call to XenGetE820Map()
On 12 July 2016 at 19:33, Andrew Fish wrote:
>
>> On Jul 12, 2016, at 9:55 AM, Ard Biesheuvel
>> wrote:
[...]
>> OK, so in summary, the AMD64 small model not only limits the relative
>> range but also the absolute placement of the code? This is
On 07/13/16 16:55, Ard Biesheuvel wrote:
> The E820EntriesCount variable in XenPublishRamRegions() may be
> referenced without being initialized on RELEASE builds, since the
> ASSERT that fires if the call to XenGetE820Map() fails is compiled
> out in that case. So initialize it to 0.
>
>
Reviewed-by: Giri P Mudusuru
> -Original Message-
> From: Fan, Jeff
> Sent: Tuesday, July 12, 2016 4:44 AM
> To: edk2-de...@ml01.01.org
> Cc: Tian, Feng ; Kinney, Michael D
> ; Mudusuru, Giri P
>
On Wed, Jul 13, 2016 at 03:29:03PM +0200, Ard Biesheuvel wrote:
> On 7 July 2016 at 19:22, Ard Biesheuvel wrote:
> > Unlike SGIs and PPIs, which are private to the CPU and are managed at
> > the redistributor level (which is also a per-CPU construct), shared
> >
Under certain circumstances, QEMU exposes the "etc/msr_feature_control"
fw_cfg file, with a 64-bit little endian value. The firmware is supposed
to write this value to MSR_IA32_FEATURE_CONTROL (0x3a), on all processors,
on the normal and the S3 resume boot paths.
Utilize EFI_PEI_MPSERVICES_PPI to
No module in OvmfPkg uses these PCDs any longer.
The first PCD mentioned is declared by OvmfPkg, so we can remove even the
declaration.
The second PCD comes from IntelFrameworkModulePkg. The module that
consumes PcdS3AcpiReservedMemorySize is called
On 13 July 2016 at 16:32, Leif Lindholm wrote:
> On Wed, Jul 13, 2016 at 03:29:03PM +0200, Ard Biesheuvel wrote:
>> On 7 July 2016 at 19:22, Ard Biesheuvel wrote:
>> > Unlike SGIs and PPIs, which are private to the CPU and are managed at
>> >
Move the permanent PEI memory for the S3 resume boot path to the top of
the low RAM (just below TSEG if the SMM driver stack is included in the
build). The new size is derived from CpuMpPei's approximate memory demand.
Save the base address and the size in new global variables, regardless of
the
In the next patch we're going to put EFI_PEI_MP_SERVICES_PPI to use.
CpuMpPei uses the following PCDs from gUefiCpuPkgTokenSpaceGuid, beyond
those already used by CpuDxe:
- PcdCpuMicrocodePatchAddress and PcdCpuMicrocodePatchRegionSize: these
control whether CpuMpPei performs microcode update.
v1: http://thread.gmane.org/gmane.comp.bios.edk2.devel/14214
v2: http://thread.gmane.org/gmane.comp.bios.edk2.devel/14471
Changes relative to v2:
- Patches 2 and 3: pick up Jeff's R-b.
- Patch 4: resolve CpuExceptionHandlerLib to PeiCpuExceptionHandlerLib
for all PEIMs (suggested by Jeff). Drop
CpuMpPei will have to place the AP startup vector in memory under 1MB. For
this, CpuMpPei borrows memory under 1MB, but it needs a memory resource
descriptor HOB to exist there even on the S3 resume path (see the
GetWakeupBuffer() function). Produce such a HOB as an exception on the S3
resume
On 8 July 2016 at 10:42, Shi, Steven wrote:
> Both GCC and LLVM 3.8 64bits support new variable argument (VA)
> intrinsics for Microsoft ABI, enable these new VA intrinsics for
> GNUC family 64bits code build. These VA intrinsics are only
> permitted use in 64bits code, so
Reviewed-by: Chao Zhang
Thanks & Best regards
Chao Zhang
-Original Message-
From: Gao, Liming
Sent: Wednesday, July 13, 2016 8:28 PM
To: edk2-de...@ml01.01.org
Cc: Yao, Jiewen; Zhang, Chao B
Subject: [PATCH v2 5/5] SecurityPkg DxeTpmMeasureBootLib: Add
Reviewed-by: Giri P Mudusuru
Fix typo during submitting patch in description: fucntion to function.
> -Original Message-
> From: Yarlagadda, Satya P
> Sent: Wednesday, July 13, 2016 6:03 AM
> To: edk2-devel@lists.01.org
> Cc: Mudusuru, Giri P
On 7 July 2016 at 19:22, Ard Biesheuvel wrote:
> Unlike SGIs and PPIs, which are private to the CPU and are managed at
> the redistributor level (which is also a per-CPU construct), shared
> interrupts (SPIs) are shared between all CPUs, and therefore managed at
> the
In FSP2.0, Boot loader should migrate its temp ram before
calling the tempramexit API to tear down the tempram. so, we don't need the
fucntion to migrate the BL TempRam in the IntelFsp2Pkg.
Cc: Giri P Mudusuru
Cc: Jiewen Yao
Contributed-under:
Use BasePeCoffLib PeCoffLoaderGetImageInfo() to check the PE/COFF image.
In V2, add specific ImageRead() to make sure the PE/COFF image content
read is within the image buffer.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao
Reviewed-by:
External PE/COFF image may not be valid and cause memory corruption.
These patches uses PeCoffLib PeCoffLoaderGetImageInfo() to check the PE format.
If this API has been used to check PE format, the addtional comments will
be added to describe PE image has been checked.
In V2, add specific
The input PeImage in TcgMeasurePeImage() has been checked.
Cc: Jiewen Yao
Cc: Chao Zhang
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao
---
Use BasePeCoffLib PeCoffLoaderGetImageInfo() to check the PE/COFF image.
In V2, add specific ImageRead() to make sure the PE/COFF image content
read is within the image buffer.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao
Reviewed-by:
The input PeImage in HashPeImage() has been checked.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao
Reviewed-by: Jiewen Yao
Reviewed-by: Chao Zhang
---
Use BasePeCoffLib PeCoffLoaderGetImageInfo() to check the PE/COFF image.
In V2, add specific ImageRead() to make sure the PE/COFF image content
read is within the image buffer.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao
Reviewed-by:
On 07/13/16 10:27, Fan, Jeff wrote:
> Laszlo,
>
> Yes. You are correct. MtrrSetAllMtrrs() could be used by BSP to make whole
> MTRR updating.
> I agree this patch will be feature drop on MtrrSetAllMtrrs() on MTRR setting
> display.
>
> I reviewed the example you listed.
> -
On 11 July 2016 at 19:05, Jordan Justen wrote:
> On 2016-07-08 01:42:41, Shi, Steven wrote:
>> GCC5 enable GCC Link Time Optimization (LTO) and code size
>> optimization (–Os) for aggressive code size improvement.
>
> Can you fix this to be a dash? (-Os)
>
>> GCC5 X64
On Wed, Jul 13, 2016 at 09:28:06AM +0200, Ard Biesheuvel wrote:
> Commit fafb7e9c110e ("ArmPkg: correct TTBR1_EL1 settings in TCR_EL1")
> introduced a symbolic constant TCR_TG1_4KB which resolves to (2 << 30),
> and ORs it into the value to be written into TCR_EL1 (if executing at
> EL1). Since
On Wed, Jul 13, 2016 at 09:28:06AM +0200, Ard Biesheuvel wrote:
> Commit fafb7e9c110e ("ArmPkg: correct TTBR1_EL1 settings in TCR_EL1")
> introduced a symbolic constant TCR_TG1_4KB which resolves to (2 << 30),
> and ORs it into the value to be written into TCR_EL1 (if executing at
> EL1). Since
Jiewen:
Current report error message is that "ERROR: Unsupported file type!" L"Only
supports DER-encoded X509 certificate and executable EFI image", because the
return status is RETURN_UNSUPPORTED. I think this error message is also fine.
Thanks
Liming
> -Original Message-
> From:
Laszlo,
Yes. You are correct. MtrrSetAllMtrrs() could be used by BSP to make whole MTRR
updating.
I agree this patch will be feature drop on MtrrSetAllMtrrs() on MTRR setting
display.
I reviewed the example you listed.
- OvmfPkg/PlatformPei/MemDetect.c-- MTRR setting will be displayed
Commit fafb7e9c110e ("ArmPkg: correct TTBR1_EL1 settings in TCR_EL1")
introduced a symbolic constant TCR_TG1_4KB which resolves to (2 << 30),
and ORs it into the value to be written into TCR_EL1 (if executing at
EL1). Since the constant is implicitly typed as signed int, and has the
sign bit set,
On 07/13/16 02:40, Fan, Jeff wrote:
> Laszlo,
>
> Even I have r-b this patch before, I have one comment now. :-)
>
> It's better to move PeiCpuExceptionHandlerLib instance from CpuMpPei to
>
> [LibraryClasses.common.PEIM]
> +
>
On 07/13/16 03:05, Ni, Ruiyu wrote:
> All of the serials, Reviewed-by: Ruiyu Ni
>
> I think it's now a PCIE world. The change #2/4 should be fine though it
> changes
> the PciBus behavior.
> #3/4 isn't conflict with the existing platform PciHotPlugInitDxe driver which
>
This patch series fixes a number of small issues in the S3 resume path.
* Remove duplicate aligned buffer allocation on S3 resume path
* Add support for MemoryMapped REGISTER_TYPE in SetProcessorRegister()
* Move XD/BTS feature detection to SmmInitHandler() to improve performance.
Jeff Fan (5):
From: Jeff Fan
InitializeMpSyncData() invokes InitializeSmmCpuSemaphores() to allocate an
aligned buffer for all locks and semaphores. However, this function is
invoked on S3 resume path again to reset mSmmMpSyncData. It causes
an additional aligned buffer to be allocated.
From: Jeff Fan
It will be set to TRUE during S3 resume.
Cc: Michael Kinney
Cc: Feng Tian
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
From: Jeff Fan
Removed EFIAPI and parameter from CheckFeatureSupported() and removed
CheckProcessorFeature() totally.
Cc: Michael Kinney
Cc: Feng Tian
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by:
From: Jeff Fan
CheckProcessorFeature() invokes MpService->StartupAllAps() to detect
XD/BTS features on normal boot path. It's not necessary and may cause
performance impact, because INIT-SIPI-SIPI must be sent to APs if APs
are in hlt-loop mode. XD/BTS feature detection is
From: Jeff Fan
REGISTER_TYPE in UefiCpuPkg/Include/AcpiCpuData.h defines a MemoryMapped
enum value. However support for the MemoryMapped enum is missing from
the implementation of SetProcessorRegister(). This patch adds support
for MemoryMapped type SetProcessorRegister().
On 07/13/16 08:20, Laszlo Ersek wrote:
> - Audit all current uses of MtrrSetAllMtrrs(), and wherever it is
> obviously called from the BSP, append the following explicit code:
>
> DEBUG_CODE (MtrrDebugPrintAllMtrrs());
Sorry, that should be
DEBUG_CODE (MtrrDebugPrintAllMtrrs ());
On 07/13/16 02:33, Jeff Fan wrote:
> MtrrSetAllMtrrs() maybe used by APs to sync BSP's MTRR settings. BSP's MTRR
> setting should be displayed if EFI_D_CACHE flag is set when MTRR updated. In
> MtrrSetAllMtrrs(), it's not necessary to display MTRR setting again due to the
> MTRR settings should be
OpenSSL 1.0.2h was released with several severity fixes at
03-May-2016 (https://www.openssl.org/news/secadv/20160503.txt).
Upgrade the supported OpenSSL version in CryptoPkg/OpensslLib to
catch the latest release 1.0.2h.
Cc: Ting Ye
Cc: David Woodhouse
76 matches
Mail list logo