On 20 August 2017 at 19:09, Ard Biesheuvel wrote:
> On 20 August 2017 at 19:08, Alan Ott wrote:
>> On 08/20/2017 01:46 PM, Ard Biesheuvel wrote:
>>>
>>> On 19 August 2017 at 22:41, Alan Ott wrote:
Extra bits are needed to accomodate all 14 SATA ports
Signed-off-by: Alan Ott
On 20 August 2017 at 19:08, Alan Ott wrote:
> On 08/20/2017 01:46 PM, Ard Biesheuvel wrote:
>>
>> On 19 August 2017 at 22:41, Alan Ott wrote:
>>>
>>> Extra bits are needed to accomodate all 14 SATA ports
>>>
>>> Signed-off-by: Alan Ott
>>> Contributed-under: TianoCore Contribution Agreement 1.0
On 08/20/2017 01:46 PM, Ard Biesheuvel wrote:
On 19 August 2017 at 22:41, Alan Ott wrote:
Extra bits are needed to accomodate all 14 SATA ports
Signed-off-by: Alan Ott
Contributed-under: TianoCore Contribution Agreement 1.0
---
Silicon/AMD/Styx/AmdStyx.dec |
On 19 August 2017 at 22:41, Alan Ott wrote:
> Extra bits are needed to accomodate all 14 SATA ports
>
> Signed-off-by: Alan Ott
> Contributed-under: TianoCore Contribution Agreement 1.0
> ---
> Silicon/AMD/Styx/AmdStyx.dec | 2 +-
> Silicon/AMD/Styx/Drivers/StyxS
Extra bits are needed to accomodate all 14 SATA ports
Signed-off-by: Alan Ott
Contributed-under: TianoCore Contribution Agreement 1.0
---
Silicon/AMD/Styx/AmdStyx.dec | 2 +-
Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c | 4 ++--
2 files changed,
5 matches
Mail list logo