Re: [edk2] [platforms: PATCH v2 08/10] Marvell/Drivers: XenonDxe: Fix UHS signalling mode setting

2017-10-27 Thread Leif Lindholm
On Fri, Oct 27, 2017 at 03:13:50AM +0200, Marcin Wojtas wrote: > This patch fixes incorrect settings for UHS mode in > SD_MMC_HC_HOST_CTRL2 register for SDR50 and SDR25, of which > the latter was missing. This field should be set to: > > 0x4 for DDR52 > 0x2 for SDR50 > 0x1 for SDR25 > 0x0 for

[edk2] [platforms: PATCH v2 08/10] Marvell/Drivers: XenonDxe: Fix UHS signalling mode setting

2017-10-26 Thread Marcin Wojtas
This patch fixes incorrect settings for UHS mode in SD_MMC_HC_HOST_CTRL2 register for SDR50 and SDR25, of which the latter was missing. This field should be set to: 0x4 for DDR52 0x2 for SDR50 0x1 for SDR25 0x0 for others. This way EmmcSwitchToHighSpeed function is on par with Linux