On Fri, Jan 30, 2015 at 12:17 AM, Ye, Ting wrote:
> Hi Franz,
>
> Thanks for providing the patch. We agree with the update and will check in
> your patch recently.
> Could you please let us know which Linux iSCSI target triggers this error? We
> may add more test items in future.
>
> Best Regar
On 2015-01-29 23:54:44, Chen Fan wrote:
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Chen Fan
> ---
> UefiCpuPkg/CpuDxe/CpuMp.c | 31 +++
> 1 file changed, 31 insertions(+)
>
> diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/Cp
Reviewed-by: Joe Peterson
From: Carsey, Jaben
Sent: Friday, January 30, 2015 8:33 AM
To: Qiu, Shumin; Peterson, Joe
Cc: edk2-devel@lists.sourceforge.net; Carsey, Jaben
Subject: [PATCH] ShellPkg: Add quotes around NSH index argument replacement
Joe and Shumin,
Can you review this?
(just flip pa
Joe and Shumin,
Can you review this?
(just flip parameter from FALSE to TRUE to automatically add quotes around ones
with spaces)
[PATCH] ShellPkg: Add quotes around NSH index argument replacement
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jaben Carsey
Shell.c.pa
Reviewed-by: Jaben Carsey
From: Qiu, Shumin
Sent: Thursday, January 29, 2015 11:57 PM
To: Carsey, Jaben
Cc: edk2-devel@lists.sourceforge.net
Subject: [edk2][Patch]ShellPkg: Fix typos.
Importance: High
Hi Jaben,
Could you help review this patch? It fix some typos in ShellPkg.
Contributed-under:
Test
Josiel W.
--
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hub for all things parallel software developmen
On 30/01/2015 11:41, tiger...@zhaoxin.com wrote:
> So, my question is:
> BIOS provides MADT table, OS will use APIC mode.
> So OS will re-configure LINT0 / LINT1 as other mode?
>
Yes. Typically LINT1 will remain NMI, while the OS will mask LINT0 and
configure the IOAPIC to deliver ISA interru
On 01/26/15 20:03, Ard Biesheuvel wrote:
> On ARM, xen_pfn_t is 64 bits but the size of a pointer is only
> 32 bits, so casting between them needs to go via (UINTN). Also
> move the xen_pfn_t cast outside the shift so that we can avoid
> shifting 64-bit quantities on 32-bit architectures, which may
On 01/26/15 20:03, Ard Biesheuvel wrote:
> Add a ArmPlatformLib instance that can deal with the self relocation
> and truly dynamic discovery of system RAM base and size.
>
> Signed-off-by: Ard Biesheuvel
> ---
>
> .../ArmVirtualizationPkg/Library/ArmXenRelocatablePlatformLib/AARCH64/MemnodePar
On 01/26/15 20:03, Ard Biesheuvel wrote:
> Allow the use of a patchable PCD for gArmTokenSpaceGuid.PcdFvBaseAddress
> by moving it from the [FixedPcd] to the [Pcd] section in the INF file of
> PlatformPeiLib.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuv
On 01/26/15 20:03, Ard Biesheuvel wrote:
> This implements a MemoryInitPeiLib instance that differs from the
> stock ArmPlatformPkg version only in the fact that it does not remove
> the memory used by the flash device (FD). The reason is that, when using
> PrePi, the DXE core is started immediatel
On 01/28/15 17:18, Ard Biesheuvel wrote:
> On 28 January 2015 at 15:13, Olivier Martin wrote:
>> Same question as last time, would it not be better to have a PCD instead of
>> hardcoded value?
>
> Ah yes, I remember reading that but failed to take it into account.
>
>> Some platforms might want
On 01/28/15 17:04, Ard Biesheuvel wrote:
> On 28 January 2015 at 15:04, Olivier Martin wrote:
>> I do not have a strong opinion on this patch.
>> It would be better to keep the dynamic PCD support in this patch. But I am
>> aware it is not possible with PrePi (I had the issue a couple of weeks ago
Hi, experts:
I have a question about CPU’s LVT configuration.
During BIOS Phase, Cpu driver will configure:
LINT0 as ExtINT, used to be compatible with 8259 PIC.
LINT1 as NMI interrupt, used to receive NMI.
So, my question is:
BIOS provides MADT table, OS will use APIC mode.
So OS will re-configu
On 01/26/15 20:03, Ard Biesheuvel wrote:
> To allow a runtime self relocating PrePi instance to discover the base
> address of the device tree at runtime, allow the use of a patchable PCD
> for gArmVirtualizationTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress.
> We will not be using the build time p
Thanks,
I understand that a custom driver should react on ExitBootSevice to perform
needed action.
Good drivers already do this.
On 30.01.2015, at 12:07, Laszlo Ersek wrote:
> On 01/30/15 09:23, Sergey Isakov wrote:
>> Dear sirs,
>>
>> Sorry for the stupid question, I am not found an explanatio
On 01/30/15 09:23, Sergey Isakov wrote:
> Dear sirs,
>
> Sorry for the stupid question, I am not found an explanation.
> If an UEFI BIOS loaded additional drivers then how to stop all of them
> at OS started?
> I may propose that OnExitBootService do this but
> DxeMain.c->CoreExitBootServices () d
Dear sirs,
Sorry for the stupid question, I am not found an explanation.
If an UEFI BIOS loaded additional drivers then how to stop all of them at OS
started?
I may propose that OnExitBootService do this but
DxeMain.c->CoreExitBootServices () does not contain such codes.
So user should do this?
Hi Franz,
Thanks for providing the patch. We agree with the update and will check in
your patch recently.
Could you please let us know which Linux iSCSI target triggers this error? We
may add more test items in future.
Best Regards,
Ye Ting
-Original Message-
From: Tian, Feng [mailto:
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chen Fan
---
UefiCpuPkg/CpuDxe/CpuMp.c | 8
1 file changed, 8 insertions(+)
diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c
index 94b72b7..453dc47 100644
--- a/UefiCpuPkg/CpuDxe/CpuMp.c
+++ b/UefiC
After the HLT instruction stops the execution of AP, an
enabled interrupt will resume execution. including including NMI
and SMI, here we introduce NMI interrupt to wake up AP with
hlt state.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chen Fan
---
UefiCpuPkg/Include/L
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chen Fan
---
UefiCpuPkg/CpuDxe/CpuMp.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c
index 453dc47..e328de7 100644
--- a/UefiCpuPkg/CpuDxe/CpuMp.c
+++ b/U
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chen Fan
---
UefiCpuPkg/CpuDxe/CpuMp.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c
index 71b62be..94b72b7 100644
--- a/UefiCpuPkg/C
nowadays, APs are busy running when installing MP protocol in
multiple processors environment. so it whould consume much power
resource unnecessary. this patchs put APs to sleep when not procedure
to run, then via sending NMI IPI by BSP to wake up AP with hlt state.
there is a proposal several mon
Hi Jaben,
Could you help review this patch? It fix some typos in ShellPkg.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qiu Shumin mailto:shumin@intel.com>>
Thanks
Shumin
ShellPkg_Typo.patch
Description: ShellPkg_Typo.patch
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