They put a Cortex M0 on the module that sits on the board, along with the
stepper driver and encoder.
There's a greater latency inside the Cortex, it will likely have to respond to
an interrupt thus have ISR latency. I presume they've got a PLL to prevent
oscillation within the final step.
It
Best option is probably to generate stepper signal from hardware timer.
2016-10-21 8:17 GMT+02:00 Danny Miller :
> The SPI comm of course has latency within a comm period.
>
> However, the pulse output must be super-fast. It supports up to 14500
> rpm, so if it's 2000steps/rev the whole step cyc
The SPI comm of course has latency within a comm period.
However, the pulse output must be super-fast. It supports up to 14500
rpm, so if it's 2000steps/rev the whole step cycle is 2ms, realistically
like maybe 1/4 of that for latency?
Danny
On 10/19/2016 11:34 PM, Nicklas Karlsson wrote:
>>>
> > ... The lag also seemed to vary with velocity.
> >
> >
> Most specifically, it was a lag in the encoder's loop to respond to
> acceleration.
> Velocity was fine, but when there is acceleration, the encoder's
> velocity didn't change for a few milliseconds, then it had to produce
> velocity g
