1. Page 82: I would hope this is no longer true (the bitfiles were fixed
sometime in 2005)
Note!: This is the intended pinout of P3. Unfortunately, in the current FPGA
configuration dis-tributed with EMC2 10 , the secondary encoders, enc-04,
enc-05, enc-06, and enc-07 are wrongly
] minor Mesa 5I20 related errors in EMC2 user manual
I will make these revisions in the manual for emc 2.2.0.
Can you tell me what the maximum valid value for the dacRate module
parameter is?
Jeff
If thats the RATE register, 65535 is the PWM/DAC maximum rate (unsigned 16
bit number)
RATE sets
emc uses this equation to get pwmRate from dacRate:
pCard16-pwmRate = dacRate * 65536 / 1000 * 1024 / 33000;
so the 33MHz SYSCLK is hardcoded at the moment.
That makes the max usable Hz value 32226, giving a pwmRate of 65534
and an actual rate of 32225.79Hz. I've updated the documentation to
] minor Mesa 5I20 related errors in EMC2 user manual
emc uses this equation to get pwmRate from dacRate:
pCard16-pwmRate = dacRate * 65536 / 1000 * 1024 / 33000;
so the 33MHz SYSCLK is hardcoded at the moment.
That makes the max usable Hz value 32226, giving a pwmRate of 65534
and an actual
Thanks for the offer. I have one, but it's not in a working PC at the
moment.
Jeff
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